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c3c9c327b7
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11 Commits

Author SHA1 Message Date
Ross Thompson
c3c9c327b7 Fixed more constraint issues in fpga. 
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
 2021-12-05 15:14:18 -06:00
Ross Thompson
5b4ff4526e Fixed a bunch of fpga issues. 2021-12-03 17:47:54 -06:00
Ross Thompson
cbb5e4440f Improved FPGA makefile and fixed timing constraints in clock converter. 2021-12-03 10:05:13 -06:00
Ross Thompson
96fb3acefd Constraints for fpga are still wrong. 2021-12-02 14:23:21 -06:00
Ross Thompson
303324d370 Added tcl commands to build the implementation. 2021-12-02 10:17:30 -06:00
Ross Thompson
e94fb2aaec Got fpga synthesis running from scripts. 2021-12-01 16:59:04 -06:00
Ross Thompson
d5f445e0fd Added make clean to fpga IP generator. 2021-11-29 18:42:28 -06:00
Ross Thompson
a528a86607 Created Makefile to manage IP generation. 2021-11-29 18:33:58 -06:00
Ross Thompson
51807379a8 Added final IP generator script (proc_sys_reset). 2021-11-29 17:43:47 -06:00
Ross Thompson
8aa87958a9 Added ddr4 generator script. 2021-11-29 15:56:57 -06:00
Ross Thompson
da4ed957aa Created tcl scripts to build 2 of the 4 xilinx IP. 2021-11-29 11:26:08 -06:00