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Author SHA1 Message Date
Katherine Parry
c34633804a cvtfp module documented 2021-10-14 15:25:31 -07:00
James E. Stine
c5b99300e7 Clean up some signals - beautification onging 2021-10-14 17:12:00 -05:00
Kip Macsai-Goren
869c35ba1c Fixed typo in imperas64mmu tests causing PMP tests not to run. 2021-10-14 13:42:24 -07:00
Skylar Litz
71397d5db9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-13 15:38:32 -07:00
Skylar Litz
4ca4e13ba2 add StallM signal back to DivStartE control 2021-10-13 15:34:40 -07:00
James E. Stine
1dba57dce7 Update to fpdivsqrt to go on posedge as it should. Also an update to 
individual regression test for TestFloat (still needs some tweaking)
 2021-10-13 17:14:42 -05:00
kipmacsaigoren
a898204c04 added outputs from synth run to test mul changes 2021-10-13 12:38:14 -05:00
bbracker
bfe972a213 gitignore new logs folder 2021-10-12 10:42:13 -07:00
bbracker
4abc6fc915 change infrastructure to expect only 6.3 million from buildroot 2021-10-12 10:41:15 -07:00
Shreya Sanghai
4424006624 added DESIGN_COMPLIER to forgotten config files 2021-10-12 10:14:04 -07:00
Katherine Parry
b79021a73e lint warnings fixed 2021-10-12 09:45:02 -07:00
Katherine Parry
539d21645f some fpu lint warnings fixed - still working on it 2021-10-11 18:32:03 -07:00
kipmacsaigoren
7873ba7867 added historical outputs folder for synth runs 2021-10-11 19:52:52 -05:00
Shreya Sanghai
0acf9fd746 made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
Shreya Sanghai
84ff2b49c7 actually added redundant mul 2021-10-11 11:29:13 -07:00
David Harris
af7903e1b2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-11 11:21:39 -07:00
David Harris
1cdc5db75d Extended lint to check rv32/64g (including fpu. Not clean yet. 2021-10-11 11:20:42 -07:00
Shreya Sanghai
a1c9ffdf2b added redundant multiplier 2021-10-11 11:20:12 -07:00
David Harris
ab6a796690 Starting to optimize multiplier 2021-10-11 11:06:07 -07:00
davidharrishmc
76e186693c Update README.md 2021-10-11 08:50:44 -07:00
David Harris
8a39f37f94 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-11 08:14:38 -07:00
David Harris
f1190b6ceb intdiv cleanup 2021-10-11 08:14:21 -07:00
davidharrishmc
fa2c6bf381 Update README.md 2021-10-11 08:13:15 -07:00
David Harris
4139f27d10 Divider FSM simplification 2021-10-10 22:24:14 -07:00
David Harris
75c17dc372 Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
James E. Stine
2b66615812 Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH 2021-10-10 15:44:01 -05:00
bbracker
13352eccda Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 13:12:44 -07:00
bbracker
161767cddd make regression expect what buildroot is actually able to reach 2021-10-10 13:12:36 -07:00
David Harris
a6c6b2b974 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:26:15 -07:00
David Harris
caf3c2de9b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:25:11 -07:00
bbracker
90ccd60790 simplify flopenrc's that didn't actually need to be flopenrc's 2021-10-10 12:25:05 -07:00
David Harris
43d92f2507 Divider cleanup 2021-10-10 12:24:44 -07:00
David Harris
6704e37597 Simplifying divider FSM 2021-10-10 12:21:43 -07:00
David Harris
4deae8019a Simplifying divider FSM 2021-10-10 12:21:36 -07:00
David Harris
2759f1fcb1 Moved & ~StallM from FSM into DivStartE 2021-10-10 11:49:32 -07:00
David Harris
635fe181f8 Moved divide iteration register names to M stage 2021-10-10 11:30:53 -07:00
David Harris
b713b6ca87 Simplified remainder for divide by 0 2021-10-10 11:20:07 -07:00
David Harris
6988c8c37c divider control signal simplificaiton 2021-10-10 10:55:02 -07:00
David Harris
c2bb0324c6 Removed negedge flops from divider 2021-10-10 10:41:13 -07:00
bbracker
2f02287f91 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 10:10:06 -07:00
bbracker
a88ae5aaff use correct string formatting function 2021-10-10 10:09:59 -07:00
David Harris
3aa9e088c8 Simplified divider sign handling 2021-10-10 08:35:26 -07:00
David Harris
39bbeefa78 renamed DivStart 2021-10-10 08:32:04 -07:00
David Harris
64ed267825 renamed DivSigned 2021-10-10 08:30:19 -07:00
Katherine Parry
77fe00947e FMA matches diagram and lint warnings fixed 2021-10-09 17:38:10 -07:00
bbracker
6fce53d146 make testbench-linux halt on some discrepancies with QEMUw 2021-10-09 17:22:30 -07:00
kipmacsaigoren
96565f9435 rename adder in fpu for synthesis 2021-10-08 17:47:54 -05:00
kipmacsaigoren
7fde7aae6e Merging new changes into the old one's I've made in the OKstate servers 2021-10-08 17:47:11 -05:00
Kip Macsai-Goren
303beaa083 updated pmp output to correspond to test changes, commented out execute tests until cache/fence interaction works fully. 2021-10-08 15:40:18 -07:00
Kip Macsai-Goren
f3058f94c6 removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions. 2021-10-08 15:33:18 -07:00