Ross Thompson
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beb954ae27
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-04 17:39:26 -05:00 |
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Ross Thompson
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e0a7abbe50
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-04 17:39:14 -05:00 |
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Ross Thompson
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294645a49f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-04 17:38:49 -05:00 |
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Ross Thompson
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494f8b94f4
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Reordered the eviction and fetch in cache so it follows a more logical order.
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2022-10-04 17:36:07 -05:00 |
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Ross Thompson
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2d063bbb2d
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Updated constraints file to work with alternate uart.
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2022-10-04 17:35:44 -05:00 |
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Ross Thompson
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18e739befc
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Modified cache lru to not have the delayed write.
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2022-10-04 15:14:58 -05:00 |
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Kip Macsai-Goren
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c18c181fc0
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fixed endianness mstatush problem, passes make, not regression
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2022-10-04 17:37:39 +00:00 |
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Kip Macsai-Goren
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3f6d05f7a2
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addded renamed file
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2022-10-04 17:37:05 +00:00 |
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Kip Macsai-Goren
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9a0b98037b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-10-04 17:33:54 +00:00 |
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Kip Macsai-Goren
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fb464b9546
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Renamed endianswap to match module name
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2022-10-04 17:33:49 +00:00 |
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Ross Thompson
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0ed0c18aa1
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Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.
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2022-10-02 16:21:21 -05:00 |
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Ross Thompson
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d08c29e3c5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-01 15:01:22 -05:00 |
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Ross Thompson
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41ab4850e1
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Disable IFU bus access on TrapM.
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2022-10-01 14:54:16 -05:00 |
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Ross Thompson
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e27fcb1577
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Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage.
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2022-09-29 18:37:34 -05:00 |
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David Harris
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657f16dfd1
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Adding start signals for integer divider to fdivsqrt
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2022-09-29 16:30:25 -07:00 |
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Ross Thompson
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2c0132aa9c
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Renamed signals in EBU.
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2022-09-29 18:29:38 -05:00 |
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cturek
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e8a869e0e7
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Added integer inputs and flags to divsqrt
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2022-09-29 23:08:27 +00:00 |
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Ross Thompson
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58d597b614
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Simplification to EBU.
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2022-09-29 18:06:34 -05:00 |
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Ross Thompson
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d81af3bca8
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Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.
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2022-09-29 11:54:03 -05:00 |
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Ross Thompson
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32449dfe97
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Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
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2022-09-28 17:39:51 -05:00 |
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Ross Thompson
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4db017dac3
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Possible fix for ifu/lsu arbiration issue.
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2022-09-27 17:24:35 -05:00 |
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Ross Thompson
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4062fe56c0
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Possible fix to the bus cache interaction.
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2022-09-27 11:34:33 -05:00 |
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Ross Thompson
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07bb11518e
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Found a hidden bug in the cache to bus fsm interlock.
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2022-09-26 17:41:30 -05:00 |
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Ross Thompson
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996c4ca8f2
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renamed ahbmulticontroller to ebu.
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2022-09-26 14:37:18 -05:00 |
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Ross Thompson
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8ed173a5f5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-26 12:49:16 -05:00 |
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Ross Thompson
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0fcc314d06
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Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
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2022-09-26 12:48:26 -05:00 |
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Kip Macsai-Goren
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e603973dff
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added xlen and endianness test edits. xlen passes but endinanness still won't make
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2022-09-26 05:03:19 +00:00 |
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Kip Macsai-Goren
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61745f9804
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added simple post processing script to give branch miss proportion in coremark log
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2022-09-26 04:51:04 +00:00 |
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David Harris
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713df785d1
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changed always_ff to always in sram1p1rw to fix testbench complaint
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2022-09-25 19:56:40 -07:00 |
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Ross Thompson
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38edbde966
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Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
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2022-09-23 11:46:53 -05:00 |
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Ross Thompson
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2eaf3af6c7
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Removed the write first sram model.
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2022-09-22 16:12:08 -05:00 |
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Ross Thompson
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cec50ce208
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The valid and dirty bits match the SRAM implementation now.
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2022-09-22 16:09:09 -05:00 |
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Ross Thompson
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b48d6b5e1f
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Solved the sram write first / read first issue. Works correctly with read first now.
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2022-09-22 14:16:26 -05:00 |
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Ross Thompson
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89e6ddfa4e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 18:24:06 -05:00 |
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Ross Thompson
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99e01dd31f
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Cleaned up the IFU and LSU around dtim and irom address calculation.
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2022-09-21 18:23:56 -05:00 |
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David Harris
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d6297a2f2e
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For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc
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2022-09-21 13:30:35 -07:00 |
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David Harris
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e49e99548a
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Fixed testbench-fp to support all again
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2022-09-21 13:19:48 -07:00 |
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David Harris
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46680b80a7
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Eliminated store after store stall when no cache; simplified divshiftcalc logic.
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2022-09-21 13:02:34 -07:00 |
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Ross Thompson
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f57b0b9950
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Updated IROMAdr logic.
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2022-09-21 12:42:43 -05:00 |
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Ross Thompson
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0add170b44
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 12:36:52 -05:00 |
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Ross Thompson
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3fb0a13fe2
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Moved other SRAMs to generic/mem.
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2022-09-21 12:36:03 -05:00 |
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David Harris
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030fb79a3c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 10:35:11 -07:00 |
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David Harris
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cb4c3ff1ce
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Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest
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2022-09-21 10:35:08 -07:00 |
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Ross Thompson
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66c45949b5
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Renamed brom1p1r to rom1p1r.
removed used file bram2p1r1w.sv.
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2022-09-21 12:31:20 -05:00 |
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Ross Thompson
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832658838d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 12:20:12 -05:00 |
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Ross Thompson
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ac864a6ca3
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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Ross Thompson
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c0884ecc63
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Modified sram1p1rw to support 3 different implementation styles.
SRAM, Read first, and Write first.
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2022-09-21 11:26:00 -05:00 |
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David Harris
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129b9343fe
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commented SpecialCase
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2022-09-21 05:02:08 -07:00 |
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David Harris
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5e1932c649
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Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc
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2022-09-21 04:55:43 -07:00 |
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David Harris
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f7d272c315
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Gated sticky bit in fdiv with SpecialCase
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2022-09-20 20:05:00 -07:00 |
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