Katherine Parry
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bea4ec078d
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variable interations implemented in radix-4 divider
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2022-07-11 18:30:21 -07:00 |
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Katherine Parry
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c56fdd7e0f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-08 12:30:50 -07:00 |
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Katherine Parry
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88b4f9b40a
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renamed signals in cvt and prostproc
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2022-07-08 12:30:43 -07:00 |
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James Stine
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99fed5d59f
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Update SRAM to /proj/wally
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2022-07-08 08:09:55 -05:00 |
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slmnemo
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e190aeb14b
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Fixed error in gpio test
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2022-07-08 02:27:16 -07:00 |
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David Harris
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8be1dafbd6
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Removed testbench code that ignores mismatch on zero signatures
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2022-07-08 09:17:31 +00:00 |
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David Harris
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87ea95e6c5
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erge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-08 09:09:07 +00:00 |
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David Harris
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5ae88dbef0
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Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
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2022-07-08 09:09:02 +00:00 |
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David Harris
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96cc66d151
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Adjusting byte writes to RAM
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2022-07-08 08:45:21 +00:00 |
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David Harris
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38ef8eebbb
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Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables
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2022-07-08 08:44:37 +00:00 |
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David Harris
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234175f236
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Removed unused swbytemask from CLINT
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2022-07-08 08:43:24 +00:00 |
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Madeleine Masser-Frye
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5608cf327a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-08 08:02:19 +00:00 |
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Madeleine Masser-Frye
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b37c0adab6
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made wally synth flow shell based
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2022-07-08 08:02:11 +00:00 |
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Madeleine Masser-Frye
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152c9fa0f3
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restore flatten
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2022-07-08 08:01:10 +00:00 |
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David Harris
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eba518625d
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makefile
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2022-07-07 16:43:03 -07:00 |
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David Harris
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7ef87777c1
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CoreMark makefile tuning
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2022-07-07 16:42:30 -07:00 |
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Katherine Parry
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b67792086c
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moved unsused division code again
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2022-07-07 16:41:26 -07:00 |
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cturek
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ccc97d6fee
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Sqrt exponents
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2022-07-07 23:34:56 +00:00 |
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Katherine Parry
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2e772dee69
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-07 16:29:44 -07:00 |
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Katherine Parry
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b1e2a1e5a1
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Revert "moved old divsqrt to unusedsrc"
This reverts commit 5dd07c76bd.
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2022-07-07 16:29:17 -07:00 |
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DTowersM
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4786fb9fd6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
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2022-07-07 23:11:35 +00:00 |
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DTowersM
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aa8580b2dc
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new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory
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2022-07-07 23:11:02 +00:00 |
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Katherine Parry
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5dd07c76bd
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moved old divsqrt to unusedsrc
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2022-07-07 16:09:56 -07:00 |
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Katherine Parry
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75a8cea4e4
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srt divider merged into fpu
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2022-07-07 16:01:33 -07:00 |
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cturek
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010ab2e90e
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Seventeen Square Root Tests
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2022-07-07 22:48:46 +00:00 |
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David Harris
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425fec0f41
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-07 22:00:59 +00:00 |
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Katherine Parry
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c581fba4aa
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modified wally shared
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2022-07-07 21:59:43 +00:00 |
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David Harris
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f865994ba1
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fixing port errors
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2022-07-07 21:57:10 +00:00 |
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Katherine Parry
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7771f7b3eb
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added load and store test
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2022-07-07 21:48:51 +00:00 |
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cturek
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269884b672
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Preprocessing for square root
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2022-07-07 21:23:30 +00:00 |
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David Harris
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f2915129ab
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Preliminary SRAM integration
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2022-07-07 19:56:20 +00:00 |
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Madeleine Masser-Frye
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c7b03978bf
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plot tuning, fo4 axis
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2022-07-07 16:44:02 +00:00 |
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David Harris
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3aa68ecfe6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-07 15:57:50 +00:00 |
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Madeleine Masser-Frye
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b883c3ad94
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-07 15:52:05 +00:00 |
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Madeleine Masser-Frye
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d06549b479
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updated synth flow to prevent runs from writing over each other's configs
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2022-07-07 15:52:01 +00:00 |
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David Harris
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bf5168873e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-07 15:51:33 +00:00 |
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Madeleine Masser-Frye
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280c1ec368
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set input delay when flop-driven, added run clock
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2022-07-07 15:50:34 +00:00 |
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slmnemo
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261248538c
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sim-buildroot-batch now runs wally-pipelined-batch
with option buildroot buildroot-no-trace to boot linux from step 0
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2022-07-06 18:06:43 -07:00 |
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David Harris
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8ae7139545
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-06 23:44:47 +00:00 |
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DTowersM
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5dfff900b1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
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2022-07-06 23:44:27 +00:00 |
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DTowersM
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67c5d66209
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added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu
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2022-07-06 23:43:57 +00:00 |
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David Harris
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21fb120aac
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-06 23:43:05 +00:00 |
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Ross Thompson
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d716c25275
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Fixed an issue with direct map cache's nextway logic.
Also found a small error in the replacement policy.
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2022-07-06 18:34:30 -05:00 |
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Madeleine Masser-Frye
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ad29e19a27
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fixed width mismatch for rv64 ieuadrM and readdatawordM
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2022-07-06 22:39:35 +00:00 |
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David Harris
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e22d6a2f9a
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Removed Sky130 libraries
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2022-07-06 13:50:11 +00:00 |
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David Harris
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529f48ed58
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-06 13:26:26 +00:00 |
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David Harris
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76302a8599
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PLIC and UART passing tests on APB
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2022-07-06 13:26:14 +00:00 |
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slmnemo
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4fa4aaa7af
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Resolved conflicts between different gpio files
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2022-07-05 18:38:52 -07:00 |
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slmnemo
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6b2125ab0e
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Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests.
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2022-07-05 18:21:17 -07:00 |
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Madeleine Masser-Frye
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52562c9190
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new priority onehot module for better area/time
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2022-07-06 00:08:59 +00:00 |
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