549 Commits

Author	SHA1	Message	Date
Ross Thompson	be6468c6d9	Icache ITLB interlock fix.	2021-06-30 19:24:59 -05:00
Katherine Parry	6216bd7172	FPU control signals changed and FMA works	2021-06-28 18:53:58 -04:00
bbracker	aa8da43743	temporarily disable PMP checking for EBU accesses.	2021-06-26 07:19:51 -04:00
bbracker	4e09793a9a	ah merge; I checked and this does pass all of regression except lints	2021-06-25 07:37:06 -04:00
bbracker	aac9b46a1f	changed SC M-to-E fowarding to W-to-E forwarding to improve critical path	2021-06-25 07:18:38 -04:00
Katherine Parry	bc8d660bc5	FPU forwarding reworked pt.1	2021-06-24 18:39:18 -04:00
bbracker	ced5039776	Revert "fixed forwarding" ... This reverts commit 0f4a4a6ade.	2021-06-24 17:39:37 -04:00
bbracker	0f4a4a6ade	fixed forwarding	2021-06-24 11:20:21 -04:00
Katherine Parry	44af47608c	fpu clean-up	2021-06-23 16:42:40 -04:00
Ross Thompson	d5063bee7d	Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.	2021-06-23 15:13:56 -05:00
Ross Thompson	5de7a46237	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-06-23 09:34:42 -05:00
David Harris	718630c378	Reduced complexity of pmpadrdec	2021-06-23 03:03:52 -04:00
David Harris	4189b2d4a7	Reduced complexity of pmpadrdec	2021-06-23 02:31:50 -04:00
David Harris	1972d83002	Refactored pmachecker to have adrdecs used in uncore	2021-06-23 01:41:00 -04:00
David Harris	6dc54acde8	renamed dmem to lsu and removed adrdec module from pmpadrdec	2021-06-22 23:03:43 -04:00
bbracker	ae0fa90450	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-22 18:28:30 -04:00
bbracker	b43a8885cd	give EBU a dedicated PMA unit as just an address decoder	2021-06-22 18:28:08 -04:00
Ross Thompson	e7d8d0b337	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-06-22 15:47:16 -05:00
Katherine Parry	9eb6eb40bf	rv64f FLW passes imperas tests	2021-06-22 16:36:16 -04:00
Kip Macsai-Goren	d6c5c61b59	Fixed mask assignment error, made usage, variables more clear	2021-06-22 13:31:06 -04:00
Kip Macsai-Goren	b78c09baed	Continued fixing fsm to work right with svmode	2021-06-22 13:29:49 -04:00
Kip Macsai-Goren	852bb9296f	updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop	2021-06-22 11:21:11 -04:00
Ross Thompson	03084a4128	Icache now uses physical lenght bits rather than XLEN.	2021-06-21 16:41:09 -05:00
Ross Thompson	8ec5b0c4f1	Improved some names in icache.	2021-06-21 16:40:37 -05:00
David Harris	29ad38fb9e	Added Physical Address and Size to PMA Checker/MMU	2021-06-21 01:27:02 -04:00
David Harris	aef408af58	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
David Harris	0a59b006ab	Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals	2021-06-20 22:59:04 -04:00
bbracker	83a1f29c37	remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR	2021-06-20 22:38:25 -04:00
Katherine Parry	26bad083ad	all rv64f instructions except convert, divide, square root, and FLD pass	2021-06-20 20:24:09 -04:00
bbracker	7aa2f0d953	make xCOUNTEREN what buildroot expects it to be	2021-06-20 09:22:31 -04:00
Ross Thompson	bb756849a7	Revert "Icache now uses physical lenght bits rather than XLEN." ... This reverts commit d4de8a54a2.	2021-06-19 08:58:34 -05:00
Ross Thompson	e4c932265d	Revert "Improved some names in icache." ... This reverts commit 22ea801edb.	2021-06-19 08:58:32 -05:00
Ross Thompson	22ea801edb	Improved some names in icache.	2021-06-18 12:22:41 -05:00
Ross Thompson	d4de8a54a2	Icache now uses physical lenght bits rather than XLEN.	2021-06-18 12:02:59 -05:00
David Harris	21a55458ca	Made MemPAdrM and related signals PA_BITS wide	2021-06-18 09:36:22 -04:00
David Harris	a3f3533cce	Changed physical addresses to PA_BITS in size in MMU and TLB	2021-06-18 09:11:31 -04:00
David Harris	cc78504ae4	Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX	2021-06-18 08:13:15 -04:00
David Harris	72d8d34e3c	allow all size memory access in CLINT; added underscore to peripheral address symbols	2021-06-18 08:05:50 -04:00
David Harris	e03912f64c	Cleaned up name of MTIME register in CSRC	2021-06-18 07:53:49 -04:00
David Harris	8357b14957	Further cleaning of PMA checker	2021-06-17 22:27:39 -04:00
David Harris	91a13999a9	Added SUPPORTED to each peripheral in each config file	2021-06-17 21:36:32 -04:00
David Harris	5e7ed4bd88	added inputs to pmaadrdec	2021-06-17 18:54:39 -04:00
David Harris	09c5e27853	Started simplifying PMA checker	2021-06-17 16:28:06 -04:00
bbracker	076469230f	added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version	2021-06-17 12:09:10 -04:00
bbracker	db0abfd36d	enable TIME CSR for 32 bit mode as well	2021-06-17 11:34:16 -04:00
bbracker	7d1469a06c	provide time and timeh CSRs based on CLINT's counter	2021-06-17 08:38:30 -04:00
bbracker	0647094e73	PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable	2021-06-17 05:19:36 -04:00
bbracker	7a652139b5	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
bbracker	6f1f585c2c	Merge remote-tracking branch 'origin/fixPrivTests' into main	2021-06-15 09:57:46 -04:00
Katherine Parry	920ff984ca	Updated FMA	2021-06-14 13:42:53 -04:00