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Author SHA1 Message Date
Rose Thompson
bc41f12195 Modified linux imperas tests to 
1. enable zicclsm
2. enable logging at 7000 ms
 2023-11-20 10:30:35 -06:00
Rose Thompson
5ac659b73e Merge branch 'main' of github.com:ross144/cvw 2023-11-18 19:01:48 -06:00
Rose Thompson
8c5f13d2e8 Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data. 2023-11-18 19:01:39 -06:00
Rose Thompson
8ddfdd44f6 bpred-sim only simulates 12 jobs at once. 2023-11-17 15:21:58 -06:00
Rose Thompson
889d685524 Fixed bugs in paraseHPMC.py 2023-11-17 12:05:22 -06:00
Rose Thompson
556fe16b0a Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters. 2023-11-17 11:21:25 -06:00
Rose Thompson
b2184c6ac0 Removed the size opt tests from the branch predictor analysis. 2023-11-15 22:35:33 -06:00
Rose Thompson
c6a24240f3 Updates to btb logger processing. 2023-11-15 16:53:44 -06:00
Rose Thompson
c2dc92b109 Added btb reference data. 2023-11-15 16:39:35 -06:00
Rose Thompson
809ac2203d Extended SeparateBranch to support both just branches and all control flow instructions. 2023-11-15 16:36:49 -06:00
Rose Thompson
7df5d34bf4 Fixed second bug in the logger script when branch logging enabled but counter logger not. 2023-11-15 14:56:02 -06:00
Rose Thompson
15eddc8069 Fixed bug in the btb branch logging. 
We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
 2023-11-15 14:51:47 -06:00
Rose Thompson
c285177507 Patched up linux imperas testbench. 2023-11-14 14:20:13 -06:00
Rose Thompson
94d4de5498 Merge branch 'main' of github.com:ross144/cvw 2023-11-14 13:54:48 -06:00
Rose Thompson
9d55f5092b Modified the device trees to include all the minor extensions. 2023-11-14 13:54:16 -06:00
Rose Thompson
0120bb8376 Fixed the imperas testbench to be compatible with the config changes. 2023-11-14 12:57:44 -06:00
Rose Thompson
33b123aa25 Added cbop to to rv32gc. 2023-11-14 10:55:22 -06:00
Rose Thompson
508c0cb188 Fixed another bug in the updated script changes. 2023-11-13 18:12:02 -06:00
Rose Thompson
a5303d25aa Merge branch 'main' of github.com:ross144/cvw 2023-11-13 18:10:35 -06:00
Rose Thompson
04cda8cb71 Fixed bugs in the updated fpga synthe script. 2023-11-13 18:10:22 -06:00
Rose Thompson
4302c0a3b0 Removed fpga config. No longer needed. 2023-11-13 17:50:29 -06:00
Rose Thompson
7f2d03df7f Modified the fpga build script to generate it's own config file rather than use the one in config/fpga. 2023-11-13 17:48:28 -06:00
Rose Thompson
b81bd35724 Towards removing the FPGA config file. 2023-11-13 17:20:26 -06:00
Rose Thompson
e7cf9de469 Reduced Arty A7 clock speed to 20Mhz to support Zicclsm. 2023-11-13 16:44:02 -06:00
Rose Thompson
ed7829dba8 Fixed bug in uncore updates which broke SDC. 2023-11-13 16:15:23 -06:00
Rose Thompson
3a495f2552 Cleanup and optimization of Zicclsm. 2023-11-13 14:28:22 -06:00
Rose Thompson
a53b9403e2 Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config. 2023-11-13 14:12:27 -06:00
Rose Thompson
17768471f8 Cleanup. 
Linux makefile
wally tracer.  probably reduce some complexity here.
 2023-11-13 14:04:43 -06:00
Rose Thompson
2f7479966b Merge branch 'Zicclsm' 2023-11-13 13:53:42 -06:00
Rose Thompson
b813fe8061 Updates to linux config files for sdc. 2023-11-13 13:53:23 -06:00
Rose Thompson
7ff89380e0 Updated buildroot to use kernel 6.6 and added dedicated qemu emulation script. 2023-11-13 12:36:32 -06:00
Rose Thompson
8860aa9af5 Cleanup. 2023-11-13 12:35:11 -06:00
Rose Thompson
534538b216 Simplification. 2023-11-10 18:39:36 -06:00
Rose Thompson
7158aa8390 Yay! Zicclsm passes my regression test now. 2023-11-10 18:28:51 -06:00
Rose Thompson
c29ef1666b Found another bug in the RTL's Zicclsm alignment. 2023-11-10 18:26:55 -06:00
Rose Thompson
fa6e53d8cf Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues. 2023-11-10 17:58:42 -06:00
Rose Thompson
2491ef0e23 Fixed some more bugs in the Zicclsm signature. 2023-11-10 17:36:10 -06:00
Rose Thompson
3245e2a99e Fixed bug in the Zicclsm test. 2023-11-10 17:34:23 -06:00
Rose Thompson
bd9a750583 Fixed spill bugs in the aligner. 2023-11-10 17:18:45 -06:00
Rose Thompson
b555620ac8 Fixed bug in the misaligned access test. 2023-11-10 17:02:15 -06:00
Rose Thompson
4b24878053 Merge branch 'main' into Zicclsm 2023-11-10 16:15:32 -06:00
Rose Thompson
329f4456b0 Missed tests.vh. 2023-11-10 16:10:10 -06:00
Rose Thompson
89bf1a5cf9 Fixed bug which broke the non Zicclsm configs. 2023-11-10 16:08:04 -06:00
Rose Thompson
5026772301
Merge pull request #463 from davidharrishmc/dev 
Dev
 2023-11-10 08:48:07 -08:00
David Harris
68115c6d6b Imperas commenting 2023-11-10 08:26:32 -08:00
David Harris
ae769e90aa Add Svadu support and SPI to imperas configuration 2023-11-10 06:27:25 -08:00
David Harris
5dbe869339
Merge pull request #460 from naichewa/main 
removed vestigial logic, added comments, deleted unused signals
 2023-11-10 05:18:57 -08:00
naichewa
fd06472de8 Cleanup 2023-11-09 16:52:55 -08:00
naichewa
2b4cf01a21 Remove old 2/4 bit logic, add comments, 
clean up unused signals
 2023-11-09 16:48:11 -08:00
David Harris
1876d5bebf Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-09 10:33:25 -08:00