Github_Repos/cvw
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386 Commits

Author SHA1 Message Date
David Harris
b173112f86 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
Ross Thompson
f1049be6c1 More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
11c44006c4 Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
Ross Thompson
8f5b5e0989 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-17 15:44:44 -06:00
David Harris
fd52915f3c Clean up warnings from Questa 2023-01-17 13:43:39 -08:00
Ross Thompson
b2676e1dd4 Somehow the imperas files spilled into the main branch. 2023-01-17 15:39:34 -06:00
David Harris
53d0d28828 csr cleanup 2023-01-13 22:12:06 -08:00
David Harris
c5358da771 csr cleanup 2023-01-13 21:25:55 -08:00
Ross Thompson
4a73018d6e Merge branch 'rastemp' 2023-01-13 18:09:50 -06:00
Ross Thompson
b26cec1ef4 Possible optimization of gshare. 
I don't believe the Writeback stage ghr is needed.
 2023-01-13 12:39:29 -06:00
Ross Thompson
14ecaabbf6 Nearly complete RVVI tracer. 
Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
 2023-01-12 18:43:39 -06:00
Ross Thompson
59b135d895 Added supervisor mode registers to tracer. 2023-01-12 17:04:41 -06:00
Ross Thompson
6500321aaf Added M CSRs to the CSRArray. 2023-01-12 16:51:51 -06:00
Ross Thompson
8981739310 added machine csr to logger. 2023-01-12 16:35:19 -06:00
Ross Thompson
f3443e2eca Added support to print the gprs. 2023-01-12 16:09:30 -06:00
Ross Thompson
0ea0e7a9e1 rvvi trace is coming alone nicely. 2023-01-12 14:46:31 -06:00
Ross Thompson
9a180f88f7 Completely stripped down imperas simulation. 
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
 2023-01-12 12:48:38 -06:00
Ross Thompson
5112ffcbc9 Stripped out all signature checking. 
Removed multiple tests loop.
Only runs 1 test now.
 2023-01-12 12:45:44 -06:00
Ross Thompson
8ee80c5d54 Created separate imperas testbench. 
Resolved logger issue with the duplicated instructions after commit.
 2023-01-12 12:07:07 -06:00
Ross Thompson
f59e1d03fc Added instruction logger. 2023-01-12 10:09:34 -06:00
Katherine Parry
4079f76a78 cleaned up all FPU files except for division 2023-01-11 22:02:30 -06:00
Ross Thompson
e3df1d3326 Restored to default configuration. 2023-01-09 00:21:45 -06:00
Ross Thompson
f643b45b97 Added branch outcome logger to testbench 2023-01-07 13:16:57 -06:00
Ross Thompson
48cf8d58b4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-06 15:18:13 -06:00
Ross Thompson
81fe08192e Added python script to post process performance counter metrics. 2023-01-06 15:15:54 -06:00
Ross Thompson
cd17d296d2 Added code to print out performance counters at end of each test. 2023-01-05 18:00:11 -06:00
Ross Thompson
f8c656f1e0 Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
Katherine Parry
fd3b967496 some commenting fixes, converter optimizations, and moves normshift into postproc 2023-01-03 15:55:30 -06:00
Katherine Parry
668c698bb4 removed ethe second bit from fma alignment shift 2022-12-30 12:07:44 -06:00
Katherine Parry
8150305919 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-30 09:56:35 -06:00
David Harris
18f19ce44d fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression 2022-12-30 06:40:25 -08:00
Katherine Parry
e5a76817df minor optimizations and renaming 2022-12-29 15:54:17 -06:00
Katherine Parry
b469831b53 one bitt removed from inital lignment shift 2022-12-28 17:46:53 -06:00
Cedar Turek
6d933a88c7 idiv passing radix 2, four copies 2022-12-27 22:10:48 -08:00
David Harris
0a0ca0ae07 cleanup 2022-12-27 21:29:36 -08:00
David Harris
d6aad0f3c3 Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M 2022-12-27 21:24:38 -08:00
David Harris
71f214df20 Moved fdivsqrtexpcalc to its own file 2022-12-26 08:45:43 -08:00
David Harris
0a067d342f Restored missing floating point load/store tests 2022-12-25 22:28:14 -08:00
Katherine Parry
66510f38af reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
Ross Thompson
b6b30533e8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-22 22:51:33 -06:00
Ross Thompson
942acb354e Closing in on icache flushed by FlushD rather than TrapM. 2022-12-22 20:19:09 -06:00
Kip Macsai-Goren
d25d699800 Added status.tvm bit test that passes make and regression 2022-12-22 14:43:22 -08:00
David Harris
a5dc09c97f Added assertion about atomics needing caches 2022-12-21 13:57:28 -08:00
Ross Thompson
a6ffb4cef3 Added timeout check to testbench. 
A watchdog checks the value of PCW.  If it does not change within 1M cycles immediately stop simulation and report an error.
 2022-12-21 09:18:00 -06:00
Ross Thompson
7a352edf13 Attempted to make a cache test. 2022-12-18 17:15:08 -06:00
Ross Thompson
9d1cb9337e Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
David Harris
3bef12b108 Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE 2022-12-15 08:23:34 -08:00
cturek
930fcbe956 Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs 2022-12-10 21:56:35 +00:00
Kip Macsai-Goren
055ca9ee37 Addded fix for 32 bit periph test and added test to regression 2022-12-06 09:56:08 -08:00
Kip Macsai-Goren
55627f40e2 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00