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Author SHA1 Message Date
Ross Thompson
b4338a5a50 Modified the testbench to not use the loggers for unsupported configurations. 2023-03-28 16:27:54 -05:00
Ross Thompson
6b58cb8d65 Merge branch 'main' of github.com:ross144/cvw 2023-03-28 16:22:26 -05:00
Ross Thompson
34dd2850e0 Disable loggers by default. 2023-03-28 16:20:45 -05:00
Ross Thompson
cef75cfe06 Now reports if there is a hit or miss. 2023-03-28 16:20:14 -05:00
Ross Thompson
a48049f6fe Restored performance counter reports. 2023-03-28 16:15:05 -05:00
Ross Thompson
7cc8d4f20c Now have logging of i/d cache addresses, but the performance counter reports are x's. 2023-03-28 16:09:54 -05:00
Ross Thompson
f2edf0ff86 Merge branch 'main' of github.com:ross144/cvw 2023-03-28 14:47:16 -05:00
Ross Thompson
69f6b291c6 Possible fix for issue 148. 
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.

I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.

This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
 2023-03-28 14:47:08 -05:00
Ross Thompson
108ad671cf Now reports i cache and d cache memory accesses. 2023-03-27 23:44:50 -05:00
Ross Thompson
5844ba8e71 Merge branch 'main' of github.com:ross144/cvw 2023-03-27 18:37:07 -05:00
Ross Thompson
510a0bb3ba First stab at the i cache logger. 2023-03-27 18:36:51 -05:00
Ross Thompson
498a17deda Added some additional details about the buildroot install. 2023-03-27 18:06:20 -05:00
Ross Thompson
4e2131066d Added buildroot instructions back to readme. moved these instructions to the docs directory. 2023-03-27 14:45:55 -05:00
Ross Thompson
8504774a11 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-27 11:55:19 -05:00
Ross Thompson
3f1bf7bece
Merge pull request #165 from davidharrishmc/dev 
Imperas linux merge
 2023-03-27 11:54:30 -05:00
David Harris
edaa306240 Removed unnecessary monitor 2023-03-27 09:52:38 -07:00
Ross Thompson
88c572d9bb Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-27 10:22:48 -05:00
David Harris
86ab90d715 Commented out setting RISCV in run-imperas-linux.sh 2023-03-27 06:34:45 -07:00
David Harris
f80abb9a75
Merge pull request #164 from eroom1966/add-linux 
Add linux
 2023-03-27 06:26:41 -07:00
eroom1966
e65cbc6636 update to allow running of ImperasDV with linux boot 
optimize performance of the tracer
 2023-03-27 09:46:16 +01:00
Lee Moore
39ac6be103
Merge branch 'openhwgroup:main' into add-linux 2023-03-27 09:44:13 +01:00
Ross Thompson
c8baffba7c Started constrains file for arty a7 fpga. 2023-03-24 20:38:13 -05:00
Ross Thompson
3fc0c4b34e Modified plic and uart to remove async reset. This removes vivado critical warning. 2023-03-24 20:37:48 -05:00
Ross Thompson
c10d98b1c8 Updated fpga constraints to remove critical warning. 2023-03-24 19:09:36 -05:00
Ross Thompson
78ab9f59af Updated GPIO signal names to reflect book. 2023-03-24 18:55:43 -05:00
Ross Thompson
1f37e6dcea Renamed controllerinputstage to controllerinput to match book. 2023-03-24 17:57:02 -05:00
Ross Thompson
fef025cb91
Merge pull request #162 from davidharrishmc/dev 
Merging spaces
 2023-03-24 17:49:26 -05:00
David Harris
0dc6f9b991 Merged ross's spacing fixes 2023-03-24 15:47:26 -07:00
David Harris
46e0841011
Merge pull request #159 from ross144/main 
Renamed signal to match book
 2023-03-24 15:34:59 -07:00
Ross Thompson
730f3ac84e Fixed all tap/space issue in RTL. 2023-03-24 17:32:25 -05:00
Ross Thompson
0511c73e22 Replaced tabs -> spaces cache. 2023-03-24 15:15:38 -05:00
Ross Thompson
1ff15c3882 Updated EBU to replace tabs with spaces. 2023-03-24 15:01:38 -05:00
David Harris
271f21d5d6
Merge pull request #161 from kipmacsaigoren/bitmanip_muxchange 
Bit Manipulation Mux Changes
 2023-03-24 11:56:59 -07:00
Kevin Kim
278a31c16b
Merge branch 'openhwgroup:main' into bitmanip_muxchange 2023-03-24 11:54:50 -07:00
Kevin Kim
eb8fe3ed17 Zero/Sign extend mux in Shifter, Zero extend mux in Bitmanip alu 2023-03-24 11:52:51 -07:00
David Harris
e294bfb357 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-24 11:41:07 -07:00
David Harris
63b1a48d8a
Merge pull request #160 from kipmacsaigoren/priv-tests 
Fixed mideleg issue in privileged tests
 2023-03-24 11:40:35 -07:00
Kip Macsai-Goren
b856698ce2 Revert "added premilinary boundary ccrossing cases" 
This reverts commit 3ce82f93c0.
 2023-03-24 11:27:41 -07:00
Kip Macsai-Goren
60b2d77c28 added working tests back into regression 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
e949d3dc4b ported fixes to 32 bit tests 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
f0027aef23 replaced inerrupt tests with allowed versions 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
3c6b856068 Added cause_s_soft_from_m_interrupt 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
3ce82f93c0 added premilinary boundary ccrossing cases 2023-03-24 11:22:39 -07:00
David Harris
a5e569245b Shifter capitalization 2023-03-24 09:01:07 -07:00
Ross Thompson
2956c11dbc Renamed ebu signal. 2023-03-24 10:51:04 -05:00
Ross Thompson
6eae7dda14
Merge pull request #157 from davidharrishmc/dev 
Merged branch fix
 2023-03-24 10:49:45 -05:00
David Harris
9f1c1958a6 Query about CondExtA 2023-03-24 08:35:33 -07:00
David Harris
34e0b3bc61 Shifter sign simplification and capitalization 2023-03-24 08:27:30 -07:00
David Harris
25a1ea7d23 FPU detect illegal instructions 2023-03-24 08:12:32 -07:00
David Harris
59f948d47c Start of EBU coverage tests 2023-03-24 08:12:02 -07:00