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Author SHA1 Message Date
bbracker
b3288beb38 update README.md to reflect new tvLinker location 2021-11-06 15:02:16 -07:00
bbracker
1597e0dac6 increase expectations for buildroot and timeout count 2021-11-06 14:57:29 -07:00
bbracker
e585a173e5 automated checkpoint generator 2021-11-06 14:37:49 -07:00
bbracker
d0ad8d3ae3 update tvLinker to new shared dir 2021-11-06 14:15:16 -07:00
bbracker
31d38286da make genCheckpoint accept instr count as argument 2021-11-06 14:14:15 -07:00
bbracker
24d3244cfe checkpoint MIDELEG support 2021-11-06 03:44:23 -07:00
bbracker
1d3d7cbe1e fix merge conflict 2021-11-05 23:42:15 -07:00
bbracker
3077769cbd checkpoints now use binary ram files 2021-11-05 22:37:05 -07:00
kipmacsaigoren
e7b25f7c95 changed number of critical paths reported to 1, added lots of internal signals and new report files. 2021-11-05 11:59:33 -05:00
davidharrishmc
f540bb13c0 fixed 64i 2021-11-03 13:49:07 -07:00
davidharrishmc
099c4e8b6b fixed 64i 2021-11-03 13:40:23 -07:00
davidharrishmc
d957d86f3b added wally-riscv-arch-test compile commands 2021-11-03 13:30:21 -07:00
Kevin
b34569c358 changed code aligner to run recursively on a root directory 
-only runs the aligner on .sv files
-runs recursively on sub-directories
 2021-11-03 10:49:34 -07:00
slmnemo
5fc12d4ae9 edited to include missing instructions 
added cd tests before cd imperas-riscv-tests to reflect new tests folder
modified cd ../addins so we can point to it from the new imperas-riscv-tests within the tests folder
added instructions so the buildroot test exists
 2021-11-03 01:50:00 -07:00
bbracker
e4cf044932 fix testbench interrupt timing 2021-11-02 21:19:12 -07:00
bbracker
730c52da23 genCheckpoint syntax fix 2021-11-01 15:31:38 -07:00
bbracker
8563c0f016 linux testgen refactor 2021-11-01 14:09:49 -07:00
David Harris
db268471b6 added some missing files 2021-11-01 13:36:07 -07:00
David Harris
0c829dd62c simplified header and footer 2021-11-01 13:24:18 -07:00
David Harris
910957704b Add3d wally32i test 2021-11-01 13:17:49 -07:00
David Harris
4b57af9cff PIPELINE test running 2021-11-01 12:44:35 -07:00
David Harris
c306884e2c Adding custom Wally test infrastructure 2021-11-01 08:48:46 -07:00
bbracker
38d26e857b fix buildroot graphical sim 2021-10-31 18:33:43 -07:00
davidharrishmc
e29c577627 Added instructions for rv64i_m/D 2021-10-30 07:34:53 -07:00
David Harris
e9244e7a85 Fixed exe2memfile parsing of weird line in arch64d test 2021-10-30 07:26:18 -07:00
David Harris
f35b31f166 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-29 22:32:08 -07:00
David Harris
717f9d48e9 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00
David Harris
f7acd31bcb rearranging testgen 2021-10-29 22:28:37 -07:00
Ross Thompson
74d0fb60ab Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-29 12:46:23 -05:00
Ross Thompson
8aad95366d Fixed the 4 way set associative pseudo LRU replacement policy. 2021-10-29 12:46:02 -05:00
kipmacsaigoren
8db0b5c06f added missing destination for copy command 2021-10-29 11:46:18 -05:00
Ross Thompson
f61fcd25a9 Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches. 2021-10-29 11:03:37 -05:00
kipmacsaigoren
220c58045d added timing through redundant multiplier to mdu timing report. 2021-10-28 22:43:58 -05:00
kipmacsaigoren
aaef7977f6 made make also save the netlist and log file to outputs 2021-10-28 22:37:25 -05:00
Ross Thompson
54c714d222 Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line. 2021-10-28 11:07:18 -05:00
bbracker
fe2bf13720 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-27 14:40:31 -07:00
bbracker
d14fa074ec checkpoint generator off-by-one error fix 2021-10-27 14:10:29 -07:00
Noah Limpert
21ea270fe2 Have replaced .* with signal names in ifu 2021-10-27 13:45:37 -07:00
koooo142857
0a33b0904d aligned all files in ifu folder 2021-10-27 12:43:55 -07:00
David Harris
e62b57e2c2 commented out some failing FPU tests 2021-10-27 11:27:34 -07:00
David Harris
24fcd9b0bd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-27 11:03:00 -07:00
David Harris
9cfb8deaab Fixed FResultSelM to select proper flags 2021-10-27 11:02:42 -07:00
davidharrishmc
726c17034b Added instructions for making rv32if device 2021-10-27 10:41:37 -07:00
David Harris
31a2346c37 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-27 10:37:46 -07:00
David Harris
0421b7af56 Changes for floating point sims 2021-10-27 10:37:35 -07:00
Ross Thompson
fed8882aec Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-27 09:59:55 -05:00
Ross Thompson
d98baf90a3 Replaced async reset flip flops with sync reset flip flops in cache and bpread. 2021-10-27 09:57:11 -05:00
bbracker
52529db40b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-26 12:43:48 -07:00
bbracker
1409dc48a8 bugfix argument passing to GDB script; remove outdated GDB script 2021-10-26 12:43:42 -07:00
David Harris
f793dd7a5e removed unused signal from wave.do 2021-10-26 09:02:22 -07:00