bbracker
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ac908bc2e4
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swapped out linux testbench signal names
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2021-07-17 14:46:18 -04:00 |
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David Harris
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2b0f8e9cf6
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Started pagetablewalker cleanup: combined state flops shared for both RV versions
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2021-07-17 02:53:52 -04:00 |
|
David Harris
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fe8910437a
|
Replaced separate PageTypeF and PageTypeM with common PageType
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2021-07-17 02:31:23 -04:00 |
|
David Harris
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622a14cbdd
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Removed more unused signals from ahblite
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2021-07-17 02:21:54 -04:00 |
|
David Harris
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52fcc47cdf
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Removed rest of HRDATAW from ahblite
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2021-07-17 02:15:24 -04:00 |
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David Harris
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1d171d7ea6
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Commented out HRDATAW logic in ebu
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2021-07-17 02:10:57 -04:00 |
|
David Harris
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d6f859da18
|
renamed or_rows.sv
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2021-07-16 20:17:03 -04:00 |
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David Harris
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f69393f197
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Reduced size of physical memory by 16 for performance
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2021-07-16 20:10:12 -04:00 |
|
Kip Macsai-Goren
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3d14d573a0
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included virtual memory tests in testbench
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2021-07-16 17:57:24 -04:00 |
|
Ross Thompson
|
e9649eb1f5
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Made furture progress in the mmu tests.
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2021-07-16 15:56:06 -05:00 |
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Ross Thompson
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965f34d78f
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Added guide for Ben to do linux conversion.
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2021-07-16 15:04:30 -05:00 |
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Ross Thompson
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abce241f68
|
Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
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2021-07-16 14:21:09 -05:00 |
|
Ross Thompson
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6ab7cd0f4d
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Updated the config so the tim has a bigger range.
|
2021-07-16 12:35:00 -05:00 |
|
Ross Thompson
|
bebc7cc5e3
|
Updated wave file.
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2021-07-16 12:34:37 -05:00 |
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Ross Thompson
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d3715acf2d
|
Fixed walker fault interaction with dcache.
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2021-07-16 12:22:13 -05:00 |
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bbracker
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e51ab63a86
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reduce number of UART ports to 1
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2021-07-16 12:42:29 -04:00 |
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bbracker
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d38109bc1c
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changed stop of linux boot from arch_cpu_idle to do_idle
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2021-07-16 12:27:15 -04:00 |
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Ross Thompson
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5ca7dc619c
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Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
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2021-07-16 11:12:57 -05:00 |
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bbracker
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f7092c60d1
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incremental linux config de-bloating
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2021-07-16 12:08:58 -04:00 |
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bbracker
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629d48f20f
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incremental linux config de-bloating
|
2021-07-16 11:33:11 -04:00 |
|
bbracker
|
0f1060ceb7
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incremental linux config de-bloating
|
2021-07-16 11:15:25 -04:00 |
|
bbracker
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fcb63a409a
|
incremental linux config de-bloating
|
2021-07-16 01:58:21 -04:00 |
|
bbracker
|
0a1aa821b8
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incremental linux config de-bloating
|
2021-07-16 01:54:36 -04:00 |
|
bbracker
|
149be959e0
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incremental linux config de-bloating
|
2021-07-16 01:43:16 -04:00 |
|
bbracker
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e5e3a60574
|
incremental linux config de-bloating
|
2021-07-16 01:33:51 -04:00 |
|
bbracker
|
7266b29656
|
incremental linux config de-bloating
|
2021-07-16 01:25:41 -04:00 |
|
bbracker
|
09de4ded87
|
incremental linux config de-bloating
|
2021-07-16 01:00:12 -04:00 |
|
bbracker
|
f7b43211ac
|
incremental linux config de-bloating
|
2021-07-16 00:46:22 -04:00 |
|
bbracker
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c5e9734851
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incremental linux config de-bloating
|
2021-07-16 00:41:18 -04:00 |
|
bbracker
|
d6a4b8ccfa
|
incremental linux config de-bloating
|
2021-07-16 00:34:41 -04:00 |
|
bbracker
|
285e5941e2
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incremental linux config de-bloating
|
2021-07-16 00:16:12 -04:00 |
|
bbracker
|
a6071f3fb0
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incremental linux config de-bloating
|
2021-07-16 00:10:31 -04:00 |
|
bbracker
|
226474051d
|
incremental linux config de-bloating
|
2021-07-15 23:53:15 -04:00 |
|
bbracker
|
0a15468fd5
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incremental linux config de-bloating
|
2021-07-15 23:30:24 -04:00 |
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bbracker
|
588a7d0341
|
incremental linux config de-bloating
|
2021-07-15 23:12:21 -04:00 |
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bbracker
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703b72fb89
|
incremental linux config de-bloating
|
2021-07-15 23:00:20 -04:00 |
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bbracker
|
847edccbd7
|
incremental linux config de-bloating
|
2021-07-15 21:33:52 -04:00 |
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bbracker
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2091a7104e
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incremental linux config de-bloating
|
2021-07-15 20:54:36 -04:00 |
|
bbracker
|
a4f9d7a6e5
|
working linux config
|
2021-07-15 18:49:54 -04:00 |
|
Kip Macsai-Goren
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ba5bb12e26
|
Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
|
2021-07-15 18:30:29 -04:00 |
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bbracker
|
58cbce940a
|
stripped down busybox a bit
|
2021-07-15 16:07:56 -04:00 |
|
Ross Thompson
|
96aa106852
|
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
|
2021-07-15 11:56:35 -05:00 |
|
Ross Thompson
|
4549a9f1c9
|
Merge branch 'main' into dcache
|
2021-07-15 11:55:20 -05:00 |
|
Ross Thompson
|
5fb5ac3d5a
|
Updated wave file.
|
2021-07-15 11:04:49 -05:00 |
|
Ross Thompson
|
c39a228266
|
Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
|
2021-07-15 11:00:42 -05:00 |
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Ross Thompson
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c954fb510b
|
Renamed DCacheStall to LSUStall in hart and hazard.
Added missing logic in lsu.
|
2021-07-15 10:16:16 -05:00 |
|
Ross Thompson
|
f234875779
|
dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
|
2021-07-14 23:08:07 -05:00 |
|
Ross Thompson
|
6163629204
|
Finally have the ptw correctly walking through the dcache to update the itlb.
Still not working fully.
|
2021-07-14 22:26:07 -05:00 |
|
Katherine Parry
|
701ea38964
|
Fixed lint warning
|
2021-07-14 21:24:48 -04:00 |
|
Ross Thompson
|
d41c9d5ad9
|
Added d cache StallW checks for any time the cache wants to go to STATE_READY.
|
2021-07-14 17:25:50 -05:00 |
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