David Harris
df7f2679d7
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
David Harris
c07ad03f9d
Initial implementation of SVNAPOT and SVPBMT does not break regression
2023-08-25 18:33:08 -07:00
Ross Thompson
b9af790b81
Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests.
2023-08-18 15:59:39 -05:00
Ross Thompson
f678133d19
Initial CMO implementation. Just adds control signals into the L1 caches.
2023-08-14 15:43:12 -05:00
Ross Thompson
3e66653f37
Cache cleanup.
2023-07-31 14:12:53 -05:00
Ross Thompson
52dc71507f
Fixed lint errors for issue #368 . Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN.
2023-07-26 15:08:01 -05:00
Ross Thompson
0063665baf
Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now.
2023-07-21 16:31:26 -05:00
Ross Thompson
37078f3d9b
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
2023-07-21 13:06:27 -05:00
David Harris
e6ba362794
Added prefetch instructions; sent cbo instructions to LSU
2023-07-02 10:55:35 -07:00
Ross Thompson
a011b7d591
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
2fc8080102
Got the srams parameterized correctly now.
2023-06-15 13:42:24 -05:00
Ross Thompson
e431f90cf3
Found a whole bunch of files still using the old `define configurations.
2023-06-15 13:09:07 -05:00
Harshini Srinath
c394f22803
Update swbytemask.sv
...
Program clean up
2023-06-12 13:37:35 -07:00
Harshini Srinath
8af3079f10
Update subwordwrite.sv
...
Program clean up
2023-06-12 13:35:27 -07:00
Harshini Srinath
c72d573e94
Update subwordread.sv
...
Program clean up
2023-06-12 13:31:54 -07:00
Harshini Srinath
086e1cb2df
Update lsu.sv
...
Program clean up
2023-06-12 13:29:18 -07:00
Harshini Srinath
45fde3082e
Update lrsc.sv
...
Program clean up
2023-06-12 13:14:36 -07:00
Harshini Srinath
a0c6000138
Update dtim.sv
...
Program clean up
2023-06-12 13:11:24 -07:00
Harshini Srinath
7a3c78a80d
Update atomic.sv
...
Program clean up
2023-06-12 13:08:54 -07:00
Harshini Srinath
70b6d01d2e
Update amoalu.sv
...
Program clean up
2023-06-12 12:54:50 -07:00
Ross Thompson
dd7c7f0a39
Completed LSU parameterization based on Lim's changes.
2023-05-26 11:26:09 -05:00
Ross Thompson
0c2a54540b
Subwordread now parameterized.
2023-05-26 11:22:44 -05:00
Ross Thompson
60bcd3d21a
Progress on LSU.
2023-05-26 10:47:09 -05:00
Ross Thompson
febb2442db
Partial parameterization into mmu.
2023-05-24 16:12:41 -05:00
Ross Thompson
e33db7f9a7
More parameterization. Copied Lim. Still no slow down.
2023-05-24 14:49:22 -05:00
David Harris
8bf9329815
Added M suffix in atomic
2023-04-24 12:19:56 -07:00
Ross Thompson
7c2512446c
Progress on bug 203.
2023-04-05 13:20:04 -05:00
David Harris
b95730e3a1
Coverage improvements in ieu, hazard units
2023-03-31 08:33:46 -07:00
Ross Thompson
69f6b291c6
Possible fix for issue 148.
...
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.
I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.
This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
2023-03-28 14:47:08 -05:00
Ross Thompson
730f3ac84e
Fixed all tap/space issue in RTL.
2023-03-24 17:32:25 -05:00
David Harris
77fb1b57f4
Fix Issue 145
2023-03-22 04:33:14 -07:00
David Harris
835381a122
Removed flq from LLEN=64
2023-03-19 10:25:04 -07:00
Ross Thompson
a27051b8a8
Updated NextAdr to NextSet.
2023-03-13 14:54:13 -05:00
Ross Thompson
e233b63752
Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10.
2023-03-12 13:21:22 -05:00
Ross Thompson
6fc157e628
Renamed PCFSpill to PCSpillF.
2023-03-06 17:50:57 -06:00
Ross Thompson
4b501f6e03
Added the i and d cache cycle counters.
2023-03-02 23:54:56 -06:00
David Harris
d2fd34efe6
Renamed DAPageFault to UpdateDA
2023-02-26 17:51:45 -08:00
David Harris
06872e3822
Adjusted DTIM to always be 512B independent of XLEN
2023-02-19 16:14:38 -08:00
David Harris
d7ae05ae8e
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-02-03 08:36:11 -08:00
David Harris
99d179dd3e
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
