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801 Commits

Author SHA1 Message Date
DTowersM
a61d1ab087 simplified coremark 2022-06-10 19:15:17 +00:00
DTowersM
d280f10a8d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-10 00:38:07 +00:00
DTowersM
4e5d7ec3d6 changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability 2022-06-10 00:37:53 +00:00
slmnemo
cc8acd947d Fixed lint error 2022-06-09 17:22:04 -07:00
David Harris
c1a40a15dd New RAM for further testing 2022-06-09 23:50:43 +00:00
stineje
d3ad512d3c Update integer division for r4 and qslc_r4a2.c 2022-06-09 16:45:13 -05:00
David Harris
5612ca7041 qslc_r4a2 generator 2022-06-09 17:26:47 +00:00
Madeleine Masser-Frye
88285c684c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-09 00:08:15 +00:00
Madeleine Masser-Frye
a54837b102 added one bit muxes for data critical synths 2022-06-09 00:06:12 +00:00
DTowersM
571eb21f41 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-08 16:28:18 +00:00
DTowersM
38382e3a11 added #1 delays to Stalls and Flushes in hazard unit 2022-06-08 16:28:09 +00:00
David Harris
b53aef33f5 Modified RAM for single-cycle latency 2022-06-08 02:06:00 +00:00
David Harris
cc06fa1c55 Cleaned bram interface 2022-06-08 01:39:44 +00:00
David Harris
f81719337e Added ahbapbbridge and cleaning RAM 2022-06-08 01:31:34 +00:00
DTowersM
1d41e98504 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-07 23:58:58 +00:00
DTowersM
3d654fd481 modified testbench.sv- now works with coremark 2022-06-07 23:58:50 +00:00
DTowersM
930c806753 cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000 2022-06-07 23:27:54 +00:00
DTowersM
4cadf139a6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-07 06:03:19 +00:00
DTowersM
fbfae61ba8 added support for 64 bit rv tests 2022-06-07 06:02:23 +00:00
Katherine Parry
b8cff98e48 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-06 16:06:54 +00:00
Katherine Parry
eb93bd46d7 fma synth warnings and errors removed 2022-06-06 16:06:04 +00:00
slmnemo
3a276f4c39 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-03 18:56:29 -07:00
slmnemo
8c3d7b404b Fixed recurrent issue with testbench where it would never stop 2022-06-03 18:56:24 -07:00
cturek
0e308cfccc Added integer division in srt, parametrized everything to work with integers and floating points, parametrized testbench. 2022-06-04 00:14:10 +00:00
DTowersM
23d524b439 testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh 2022-06-03 22:07:14 +00:00
Madeleine Masser-Frye
2383ca4f53 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-03 21:08:49 +00:00
Madeleine Masser-Frye
6c6a12cfd5 added muxes and inv, fixed priority encoder 2022-06-03 21:03:13 +00:00
Katherine Parry
b785b6a9bc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-03 15:34:27 +00:00
Katherine Parry
5ae63f913a fixed compilation errors 2022-06-03 15:34:17 +00:00
slmnemo
0011a1b269 Changed NO_SPOOFING from 0 to 1 in buildroot-no-trace to better facilitate wally booting linux without following QEMU's trace 2022-06-03 04:55:14 -07:00
Katherine Parry
019994c802 removed some debuging code accedentally pushed 2022-06-02 22:45:19 +00:00
Katherine Parry
dfec6bda8a added rv64fpquad 2022-06-02 22:10:00 +00:00
Katherine Parry
39101fcbb3 added config rv64fpquad 2022-06-02 22:09:11 +00:00
David Harris
12399ba924 renamed sim-fp to sim-testfloat 2022-06-02 15:05:29 -07:00
Katherine Parry
c5bde75e30 added createallvectors 2022-06-02 21:56:05 +00:00
slmnemo
b35824eadd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-02 12:54:08 -07:00
Katherine Parry
ccda4c771e fpu paramaterized - except fdivsqrt 2022-06-02 19:50:28 +00:00
slmnemo
568b83a647 Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do" 
This reverts commit 7d2bfb6db8.
 2022-06-02 12:45:21 -07:00
slmnemo
40abe59d33 Revert "Fixed buildroot by adding a second ." 
This reverts commit 0982417054.
 2022-06-02 12:43:59 -07:00
slmnemo
581c950193 Revert "Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py" 
This reverts commit 05d14bdb3c.
 2022-06-02 12:41:01 -07:00
slmnemo
74319c2af6 Revert "Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace" 
This reverts commit a5490c7096.
 2022-06-02 12:40:46 -07:00
David Harris
9065b684f8 Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit 2022-06-02 09:37:59 -07:00
David Harris
62865d9398 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-02 15:48:36 +00:00
David Harris
7cf5d481c0 Cleaned up comments in controller 2022-06-02 15:48:33 +00:00
David Harris
9cd6b309b4 Cleaned up test cases in testbench 2022-06-02 08:44:28 -07:00
David Harris
129fab3794 Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
slmnemo
61f077f62c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-02 02:52:03 +00:00
slmnemo
35caa03e46 Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files 2022-06-02 02:51:51 +00:00
Katherine Parry
74b549ddc8 paramerterized some small fma units 2022-06-01 23:34:29 +00:00
DTowersM
4fbce9fc45 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-01 21:00:51 +00:00