8 Commits

Author	SHA1	Message	Date
Rose Thompson	34631c54d3	Get's the fpga building again after the git history rewrite.	2023-12-14 17:08:25 -06:00
Rose Thompson	cdd21d6635	Added menvcfg to debugger for checking what linux has configured.	2023-11-19 13:44:22 -06:00
Ross Thompson	a89a1e675c	Merge branch 'boot' into mergeBoot ... Merges Jacob's new sdc controller into wally.	2023-07-21 17:43:45 -05:00
Jacob Pease	40f81d5da6	The Vivado-RISC-V SDC works. Wally is now booting through it.	2023-05-26 15:42:33 -05:00
Ross Thompson	576d37eb8c	Updated fpga constraints to remove critical warning.	2023-03-24 19:09:36 -05:00
Jacob Pease	f2e4274c9c	Fixed debug signal names. Builds on the fpga. Bug in the crossbar.	2023-02-16 17:33:21 -06:00
Jacob Pease	293cc88bd9	Added extra core signal to mark_debug.txt. Modified wally.tcl	2023-01-23 17:00:24 -06:00
Ross Thompson	25bd2e4670	Removed mark_debug vivado directive from source code. ... Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger. Files output to temporary directory.	2023-01-20 19:43:18 -06:00