David Harris
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72c1cc33f5
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Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
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2021-09-15 13:14:00 -04:00 |
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Ross Thompson
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150a73d6cf
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Set associate icache working, but way 0 is never written.
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2021-09-07 12:46:16 -05:00 |
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Ross Thompson
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d430659983
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fixed the read timer issue but we still have problems with interrupts and i/o devices.
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2021-08-06 10:16:06 -05:00 |
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David Harris
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20744883df
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flag for optional boottim
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2021-07-20 14:46:37 -04:00 |
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David Harris
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c117356432
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Parameterized I$/D$ configurations and added sanity check assertions in testbench
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2021-07-20 08:57:13 -04:00 |
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Ross Thompson
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07c47f0034
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Restored TIM range.
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2021-07-19 21:17:31 -05:00 |
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David Harris
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b2f7952b3d
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Added cache configuration to config files
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2021-07-19 18:19:46 -04:00 |
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David Harris
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4729a72167
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Updated FMA1 with parameterized size
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2021-07-18 20:40:49 -04:00 |
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David Harris
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f69393f197
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Reduced size of physical memory by 16 for performance
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2021-07-16 20:10:12 -04:00 |
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Ross Thompson
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6ab7cd0f4d
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Updated the config so the tim has a bigger range.
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2021-07-16 12:35:00 -05:00 |
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Ross Thompson
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a314b3cf68
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restored rv64ic config back to full sized dtim.
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2021-07-13 11:18:54 -05:00 |
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Ross Thompson
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9fe6190763
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Team work on solving the dcache data inconsistency problem.
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2021-07-12 23:46:32 -05:00 |
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David Harris
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6b9cfe90d8
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Added ASID & Global PTE handling to TLB CAM
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2021-07-04 17:52:00 -04:00 |
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David Harris
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c897bef8cd
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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Ross Thompson
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46831035fb
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-07-02 13:56:49 -05:00 |
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David Harris
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cd6cabac2f
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Optimized PMP checker logic and added support for configurable number of PMP registers
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2021-07-02 11:05:25 -04:00 |
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Kip Macsai-Goren
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1485d29dde
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Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
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2021-06-24 20:01:11 -04:00 |
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bbracker
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83a1f29c37
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
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2021-06-20 22:38:25 -04:00 |
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David Harris
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72d8d34e3c
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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09c5e27853
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Started simplifying PMA checker
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2021-06-17 16:28:06 -04:00 |
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David Harris
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e231fc6b00
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More verilator fixes, but bpred is broken
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2021-06-09 21:03:03 -04:00 |
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David Harris
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4bd7058456
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More PMP entries
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2021-06-08 15:33:06 -04:00 |
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David Harris
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9a17556de4
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Start to parameterize number of PMP Entries
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2021-06-08 15:29:22 -04:00 |
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Kip Macsai-Goren
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fcb9b1f0e1
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working version with new mmu comments, old boottim values
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2021-06-08 15:20:25 -04:00 |
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David Harris
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cfe5c27946
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Resized BOOT TIM to 1 KB
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2021-06-08 14:04:32 -04:00 |
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David Harris
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b37bcc8e38
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Continued merge
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2021-06-07 12:49:47 -04:00 |
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David Harris
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1e67db2f0c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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David Harris
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95cc70295b
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Merge difficulties
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2021-06-07 09:50:23 -04:00 |
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David Harris
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8bbabb683d
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Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
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Kip Macsai-Goren
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b99b5f8e0e
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moved privilege dfinitions into wally-constants, upgraded relevant includes
|
2021-06-04 17:55:07 -04:00 |
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David Harris
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b836679ae1
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Started MMU
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2021-06-04 11:59:14 -04:00 |
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David Harris
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a61411995a
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moved shared constants to a shared directory
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2021-06-03 22:41:30 -04:00 |
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Kip Macsai-Goren
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06cf3a8403
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Edited and added constants to support SV48
|
2021-06-01 17:49:45 -04:00 |
|
James E. Stine
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bccdd2c137
|
Updates to muldiv.sv for 32-bit div/rem
|
2021-06-01 15:31:07 -04:00 |
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Katherine Parry
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71e4a10efb
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FMV.D.X imperas test passes
|
2021-05-20 22:17:59 -04:00 |
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James E. Stine
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f407bee5ae
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Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
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2021-05-18 13:48:44 -05:00 |
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Katherine Parry
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409438bc95
|
floating point infinite loop removed from imperas tests
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2021-05-18 10:42:51 -04:00 |
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Shriya Nadgauda
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0be6b81df9
|
finishing merge conflict changes
|
2021-05-03 22:15:05 -04:00 |
|
Shriya Nadgauda
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52e0b703b7
|
merge conflict fixes
|
2021-05-03 22:12:30 -04:00 |
|
Shriya Nadgauda
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0282aebec7
|
updated pipeline tests
|
2021-05-03 22:07:36 -04:00 |
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Ross Thompson
|
893e03d55b
|
Fixed memory size in configs for rv32ic and rv64ic.
Removed warning on call to $fscanf.
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2021-04-29 17:36:46 -05:00 |
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Ross Thompson
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14a69c1d06
|
Added the ability to exclude branch predictor.
|
2021-04-26 14:27:42 -05:00 |
|
bbracker
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c796547156
|
greatly improved PLIC register interface
|
2021-04-22 11:22:01 -04:00 |
|
Noah Boorstin
|
5902637632
|
buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
|
2021-04-17 14:44:32 -04:00 |
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bbracker
|
11cf251378
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-04-15 21:09:27 -04:00 |
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bbracker
|
195cead01c
|
working GPIO interrupt demo
|
2021-04-15 21:09:15 -04:00 |
|
Domenico Ottolia
|
a149f2f3d8
|
Add support for vectored interrupts
|
2021-04-15 19:13:42 -04:00 |
|
Shreya Sanghai
|
75caa65df1
|
Cherry Pick merge of Shreya's localhistory predictor changes into main.
fixed minor bugs in localHistory
|
2021-04-15 09:04:36 -05:00 |
|
Thomas Fleming
|
e807f5d771
|
Implement support for superpages
|
2021-04-08 02:44:59 -04:00 |
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bbracker
|
ce7b2314ef
|
Yee hoo first draft of PLIC plus self-checking tests
|
2021-04-04 06:40:53 -04:00 |
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