Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
6,039 Commits 5 Branches 2 Tags 53 MiB
a1ce7fe321
Commit Graph

6039 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
James Stine
e60b49952e Add correction for regression on Sail due to bug in recent release. This hash is known to work (verified by Stine/Thompson). May remove later if Sail ever gets fixed 2023-03-21 08:36:30 -05:00
David Harris
34457f68ec Commented out failing tests related to sip and sie 2023-03-21 05:51:43 -07:00
David Harris
376bbcc71d Renamed intdivrestoring to div 2023-03-21 05:51:02 -07:00
David Harris
0fd385e5de Renamed intdivrestoring to div 2023-03-20 16:22:06 -07:00
David Harris
67072b89e9
Update LICENSE to Soldered 2023-03-20 16:05:36 -07:00
Kevin Kim
73fbc21aab formatting 2023-03-20 14:25:05 -07:00
Kevin Kim
37b73ea42e more structural mux changes 2023-03-20 14:23:54 -07:00
Kevin Kim
7a6d1ab393 added bitmanip 64 tests to updated regression script 
+ alu structural mux changes
 2023-03-20 14:19:39 -07:00
Kevin Kim
728be29ce3 formatting 2023-03-20 13:09:49 -07:00
Kevin Kim
07a43e1935 Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-20 13:06:10 -07:00
David Harris
0ecde4ab4f formatting cleanup 2023-03-20 12:45:10 -07:00
David Harris
6cc341a464
Merge pull request #144 from ross144/main 
Fixed bug in tool chain install script
 2023-03-20 10:40:44 -07:00
Ross Thompson
50a78fb674 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-20 11:52:18 -05:00
Ross Thompson
69d9bde358 Fixed bug in the tool chain install script. 2023-03-20 11:52:10 -05:00
Kevin Kim
9e5360e31f format + min/max structural mux 2023-03-20 09:37:57 -07:00
David Harris
471305bda0 Eliminate transitions to FLUSH and WRITEBACK in cachefsm for READ_ONLY_CACHE 2023-03-19 10:41:47 -07:00
David Harris
ab095de4b5 Ignore more log files left from ImperasDV 2023-03-19 10:26:53 -07:00
David Harris
8f3397df01 Renamed coverage-exclusions-rv64gc 2023-03-19 10:26:09 -07:00
David Harris
835381a122 Removed flq from LLEN=64 2023-03-19 10:25:04 -07:00
David Harris
563f243de3 Improved coverage reporting 2023-03-19 10:24:35 -07:00
David Harris
02e7e7d011 Added comments about PMP checker fixes when test cases will be ready to initialize PMP before entering user mode 2023-03-19 05:46:34 -07:00
David Harris
031cc6967a Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression. 2023-03-18 10:10:58 -07:00
David Harris
70e4c71f41 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-18 09:24:37 -07:00
David Harris
08ce265420 Replaced FenceM with InvalidateICacheM for event counting of fence.i 2023-03-18 09:24:31 -07:00
Mike Thompson
70d5b267ec
Merge pull request #140 from ross144/main 
Added notes on linux image generation
 2023-03-17 09:16:14 -04:00
Ross Thompson
e8d149df5e Merge branch 'main' of github.com:ross144/cvw into main 2023-03-17 00:48:04 -05:00
Ross Thompson
b5fa5bb47a Added notes on how to run QEMU to generate linux image. 2023-03-17 00:47:52 -05:00
Mike Thompson
112967142c
Merge pull request #139 from ross144/main 
Updates for book
 2023-03-14 15:44:59 -04:00
Ross Thompson
407b3c488d Book updates. 2023-03-14 13:09:50 -05:00
Ross Thompson
8d1a7154c2
Merge pull request #138 from eroom1966/main 
Fix MISA RO and UART addresses
 2023-03-13 23:32:56 -05:00
Ross Thompson
a27051b8a8 Updated NextAdr to NextSet. 2023-03-13 14:54:13 -05:00
Ross Thompson
cb019f9aed Updated CAdr to CacheSet. 2023-03-13 14:53:00 -05:00
Ross Thompson
c18a626abe More accurate c model gshare results. 2023-03-13 13:54:04 -05:00
Ross Thompson
ef2c5ce6a7 On our way to finish the C reference data collection. 2023-03-13 13:32:09 -05:00
Ross Thompson
77fe3c5546 Merge branch 'main' of github.com:ross144/cvw into main 2023-03-13 13:30:49 -05:00
Ross Thompson
c57e2a2140 Added reference data. 2023-03-13 13:30:43 -05:00
Ross Thompson
2d49c4582c Modified branch logger to indicate when the warmup period is done. 
The branch-predictor-simulator also changed to support this.
 2023-03-13 13:26:27 -05:00
eroom1966
0d260accb4 Fix MISA RO and UART addresses 
It appears on inspection that the MISA register is read only in Wally
In which case this has now also been set in the ImperasDV representation
Also the Addresss for the UART R/W privileges are corrected
 2023-03-13 11:07:19 +00:00
Ross Thompson
0441e3b736 Created script to batch processes all the embench branch outcomes into C model branch prediction rate. 2023-03-12 23:15:44 -05:00
Ross Thompson
755b1bfe53 Renamed script to parse branch.log 2023-03-12 22:40:59 -05:00
Ross Thompson
ae42150519 Added script to separate branch.log into separate logs for each benchmark. 2023-03-12 17:58:36 -05:00
Ross Thompson
568d0031d2 Modified the branch log to include markers for the start and end of tests with exclusion of warmup period. 2023-03-12 17:15:56 -05:00
Ross Thompson
ede9d49ce4 Changes BTA to BPBTA. 2023-03-12 14:36:46 -05:00
Ross Thompson
e233b63752 Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10. 2023-03-12 13:21:22 -05:00
Kevin Kim
bc9cd4a26e more checks in bitmanip decode 2023-03-10 17:17:24 -08:00
Kevin Kim
869c7283e8 formatting 2023-03-10 14:32:01 -08:00
Kevin Kim
827cf567e6 removed redundant convinvb signal 2023-03-10 14:18:24 -08:00
Kevin Kim
a5841c6fb2 removed redundant condinvb mux 2023-03-10 14:17:38 -08:00
Ross Thompson
23f6d58247
Merge pull request #137 from davidharrishmc/dev 
Fixes to wally-batch for coverage
 2023-03-10 15:36:24 -06:00
David Harris
a1ffff57ba Fixes to wally-batch for coverage 2023-03-10 13:33:32 -08:00