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Author	SHA1	Message	Date
Ross Thompson	85d510e315	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-01 10:50:38 -06:00
Ross Thompson	6c3109287d	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-01 10:50:24 -06:00
Ross Thompson	73edd50120	Updated fpga's bootloader to reflect the changes to the gpio address change.	2022-02-01 10:43:24 -06:00
David Harris	9770fbac70	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-31 22:58:37 +00:00
David Harris	96a0baade4	Removed soc_flow	2022-01-31 22:58:33 +00:00
Ross Thompson	2b71d48160	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-31 16:32:24 -06:00
Ross Thompson	1f0821da0d	IFU and LSU now share the same busdp module.	2022-01-31 16:25:41 -06:00
Ross Thompson	86bac2a083	partial ifu cleanup.	2022-01-31 16:08:53 -06:00
Kip Macsai-Goren	4b94cf9a43	Renamed test library	2022-01-31 20:11:21 +00:00
Kip Macsai-Goren	4d951923f4	updated minfo test to account for no mconfigptr	2022-01-31 20:11:21 +00:00
Kip Macsai-Goren	14933a7231	fixed CSR read-only test to have correct output	2022-01-31 20:11:21 +00:00
Ross Thompson	e4ee630a3e	cleanup.	2022-01-31 13:29:04 -06:00
Ross Thompson	5ce8dd60c5	Fixed modelsim warning with linux simulation.	2022-01-31 12:57:02 -06:00
Ross Thompson	c9a163b8fd	Repaired linux-wave.do	2022-01-31 12:54:18 -06:00
Ross Thompson	4422e2f91c	Repaired wavefile and fixed modelsim warning.	2022-01-31 12:34:17 -06:00
Ross Thompson	c2b2fae98d	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-31 12:17:37 -06:00
Ross Thompson	f4e62bcb54	Cleanup busdp.	2022-01-31 12:17:07 -06:00
Ross Thompson	31da37dd0f	Moved lsu virtual memory logic into separate module.	2022-01-31 11:56:03 -06:00
Ross Thompson	9cd502d0af	Encapsulated dtim.	2022-01-31 11:23:55 -06:00
Ross Thompson	c939eb20eb	Removed unused signals in the LSU.	2022-01-31 10:35:35 -06:00
Ross Thompson	5fe30ff8a9	Moved atomic logic to own module.	2022-01-31 10:28:12 -06:00
Ross Thompson	a4f6653cd8	Encapsulated the bus data path into a separate module.	2022-01-31 10:15:48 -06:00
Kip Macsai-Goren	242b27705d	added machine info test that uses new test library	2022-01-31 05:54:43 +00:00
Kip Macsai-Goren	3c61d6eec2	tentatively remade test lib to use macros for more flexibility	2022-01-31 05:54:43 +00:00
Kip Macsai-Goren	ee982c7588	converted library to header file for RISCV test compliance	2022-01-31 05:54:43 +00:00
Kip Macsai-Goren	9e3b25c940	updated tests to use test title instead of number encoding	2022-01-31 05:54:42 +00:00
James Stine	d4ea8c6ac1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-30 21:03:24 -06:00
James Stine	2405454c85	Change DC script to not do a full synthesis but partial synthesis until I configure to be more optimized	2022-01-30 21:02:41 -06:00
David Harris	090533cfe9	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
David Harris	3016b46d65	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-31 00:59:49 +00:00
David Harris	71f7d66dbf	gitmodules	2022-01-31 00:59:44 +00:00
James Stine	af8aa56a67	Add synthesis using DC shell back into repository	2022-01-30 17:35:15 -06:00
James Stine	00619eda07	Add synthesis using DC shell back into repository	2022-01-30 17:34:56 -06:00
Ross Thompson	ac50a36aac	LSU and IFU cleanup.	2022-01-28 15:26:06 -06:00
Ross Thompson	2e00186eea	Updated wave.do to match the ifu/lsu changes.	2022-01-28 14:37:15 -06:00
Ross Thompson	42d60235f0	Clean up of mmu instances in IFU and LSU.	2022-01-28 14:02:05 -06:00
Ross Thompson	c5e0024e9f	Moved spills to own module.	2022-01-28 13:40:35 -06:00
Ross Thompson	06209c417f	Cleaned up the InstrMisalignedFault.	2022-01-28 13:19:24 -06:00
Ross Thompson	3b31d8f8fb	Updated debug2 ila signal names.	2022-01-28 11:43:49 -06:00
James Stine	8fd975da74	Remove book_flow to add back later - will add synthDC back within 30m	2022-01-28 08:18:30 -06:00
David Harris	6dfeade41b	Added math.h to fir.c	2022-01-28 00:26:06 +00:00
Ross Thompson	862bf2faae	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
Ross Thompson	d15cb64bdf	Relocated the misalignment faults.	2022-01-27 16:03:00 -06:00
David Harris	30cc27e719	IFU cleanup	2022-01-27 17:18:55 +00:00
David Harris	5ab06fef20	IFU cleanup	2022-01-27 16:41:57 +00:00
David Harris	bdd5796f3a	Optimized out second adder from IFU for PC+2	2022-01-27 16:06:24 +00:00
David Harris	7f91170bab	Comments in LSU code about restructuring	2022-01-27 15:53:59 +00:00
Ross Thompson	b44f57b6b5	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-27 08:45:33 -06:00
Ross Thompson	284d671da3	Increased number of concurrent tests.	2022-01-27 08:45:25 -06:00
David Harris	448acedd8b	Set up rv32emc config	2022-01-27 14:37:58 +00:00