mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Add synthesis using DC shell back into repository
This commit is contained in:
James Stine
parent
8fd975da74
commit
00619eda07
78
synthDC/.synopsys_dc.setup
Executable file
78
synthDC/.synopsys_dc.setup
Executable file
@ -0,0 +1,78 @@
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# Search Paths
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set CURRENT_DIR [exec pwd]
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set search_path [list "./" ]
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set s8lib ../addins/sky130_osu_sc_t18/18T_ms/lib
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lappend search_path $s8lib
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# Synthetic libraries
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set synthetic_library [list dw_foundation.sldb]
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# Set OKSTATE standard cell libraries
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set target_library [list]
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lappend target_library sky130_osu_sc_18T_ms_TT_1P8_25C.ccs.db
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# Set Link Library
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set link_library "$target_library $synthetic_library"
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# Set up DesignWare cache read and write directories to speed up compile.
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set cache_write ~
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set cache_read $cache_write
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# Tell DC where to look for files
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lappend search_path ./scripts
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lappend search_path ./hdl
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lappend search_path ./mapped
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# Set up User Information
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set company "Oklahoma State University"
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set user "James E. Stine"
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# Alias
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alias ra report_area
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alias rt report_timing
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alias rc {report_constraint -all_violators}
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alias sf set_flatten
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alias ss set_structure
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alias rco report_compile_options
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alias cs compile -scan
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alias csi compile -scan -incr -map high
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alias h history
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history keep 100
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alias all_gone {remove_design -designs}
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alias page_on {set sh_enable_page_mode true}
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alias page_off {set sh_enable_page_mode false}
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# specify directory for intermediate files from analyze
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define_design_lib DEFAULT -path ./analyzed
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# suppress Driving cell warning
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suppress_message {UID-401}
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########### Source Useful Tcl Procedures ###########
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foreach _file [glob -nocomplain ./tcl_procs/*.tcl] {
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source $_file
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}
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############# Enable line editing in 2004.12 ###########
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set sh_enable_line_editing true
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############# Setup the view utility ###########
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proc view {args} {
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redirect tmpfile1212 {uplevel $args}
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# Without redirect, exec echos the PID of the new process to the screen
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redirect /dev/null {exec ./tcl_procs/view.tk tmpfile1212 "$args" &}
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}
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alias vrt {view report_timing -nosplit}
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alias vrtm {view report_timing -nosplit -delay min}
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alias vman {view man}
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34
synthDC/Makefile
Executable file
34
synthDC/Makefile
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#
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# Makefile for synthesis
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#
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NAME := synth
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VARIANT := 18T_ms
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default:
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@echo "Basic synthesis procedure for OSU/HMC/UNLV:"
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@echo " adapt Makefile to your liking..."
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@echo
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synth:
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@sed -i 's/18T_ms/${VARIANT}/g' scripts/synth.tcl
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@sed -i 's/18T_ms/${VARIANT}/g' .synopsys_dc.setup
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@echo "DC Synthesis"
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@mkdir -p reports
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@mkdir -p mapped
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dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(NAME).out
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# @cp mapped/*.sdc ../../outputs/
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# @cp mapped/*.vh ../../outputs/
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# @sed -i 's/${VARIANT}/18T_ms/g' scripts/synth.tcl
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# @sed -i 's/${VARIANT}/18T_ms/g' .synopsys_dc.setup
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clean:
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rm -rf alib-52 WORK mapped unmapped reports analyzed $(NAME).out
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mkdir mapped unmapped reports
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rm -f hdl/*
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rm -f default.svf
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rm -f command.log
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rm -f filenames*.log
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34
synthDC/README.md
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34
synthDC/README.md
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This subdirectory contains synthesis scripts for use with Synopsys
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Design Compiler (DC). The scripts are separated into two distinct
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sections: user and technology setups. The technology setup is found
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in .synopsys_dc.setup file. Key items within this technology setup
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are the location of the PDK and standard cell libraries.
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We are using the Skywater Technology 130nm process for the synthesis.
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The Oklahoma State University standard-cell libraries for this process
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are located via the target_library keyword. There are currently three
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versions of the standard-cell libraries available (see
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http://stineje.github.io) for dowload locations. Currently, the TT 18
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track OSU standard-cell library is utilized.
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There are other useful elements within the technology setup file, as
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well. These include user information as well as search path
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information. Good tool flows usually rely on finding the right files
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correctly and having a search path set correctly is importantly.
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The user setup is found in two main areas. The scripts/ and hdl/
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directories. The scripts directory contains a basic DC synthesis Tcl
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script that is involved when synthesis is run. Please modify this
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synth.tcl file to add information about PPA and information about your
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design (e.g., top-level name, SV files). The SV is found within the
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hdl/ subdirectory. Just put all your synthesis-friendly files in this
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directory or allude to the correct location in the synthesis Tcl
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script.
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After synthesis completes, always check your synthesis log file that
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will be called synth.log. Good tool flow starts and ends with
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understanding what is happening during a specific part of the flow.
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This can only be done through interpreting what the Electronic Design
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Automation (EDA) tool is doing. So, always check this file for any
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possible warnings or errors after completion. All output of synthesis
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is found in the reports/ subdirectory.
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184
synthDC/scripts/synth.tcl
Executable file
184
synthDC/scripts/synth.tcl
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@ -0,0 +1,184 @@
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#
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# Main Synopsys Flow
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# james.stine@okstate.edu 26 Jan 2022
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#
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# Config
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set hdl_src "../pipelined/src"
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eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {hdl/}
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eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {reports/}
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eval file copy [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
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eval file copy [glob ${hdl_src}/*/*.sv] {hdl/}
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eval file copy [glob ${hdl_src}/*/flop/*.sv] {hdl/}
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# Verilog files
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set my_verilog_files [glob hdl/*]
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# Set toplevel
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set my_toplevel wallypipelinedcore
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# Set number of significant digits
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set report_default_significant_digits 6
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# V(HDL) Unconnectoed Pins Output
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set verilogout_show_unconnected_pins "true"
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set vhdlout_show_unconnected_pins "true"
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#
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# Due to parameterized Verilog must use analyze/elaborate and not
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# read_verilog/vhdl (change to pull in Verilog and/or VHDL)
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#
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define_design_lib WORK -path ./WORK
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analyze -f sverilog -lib WORK $my_verilog_files
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#
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# Added if you had any VHDL
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# analyze -f vhdl -lib WORK $my_vhdl_files
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#
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elaborate $my_toplevel -lib WORK
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# Set the current_design
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current_design $my_toplevel
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link
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# Reset all constraints
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reset_design
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# Set Frequency in [MHz] or [ps]
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set my_clock_pin clk
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set my_clk_freq_MHz 10
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set my_period [expr 1000 / $my_clk_freq_MHz]
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set my_uncertainty [expr .1 * $my_period]
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# Create clock object
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set find_clock [ find port [list $my_clock_pin] ]
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if { $find_clock != [list] } {
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echo "Found clock!"
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set my_clk $my_clock_pin
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create_clock -period $my_period $my_clk
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set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
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} else {
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echo "Did not find clock! Design is probably combinational!"
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set my_clk vclk
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create_clock -period $my_period -name $my_clk
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}
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# Partitioning - flatten or hierarchically synthesize
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#ungroup -flatten -simple_names { dp* }
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#ungroup -flatten -simple_names { c* }
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#ungroup -all -flatten -simple_names
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# Set input pins except clock
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set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
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# Specifies delays be propagated through the clock network
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set_propagated_clock [get_clocks $my_clk]
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# Setting constraints on input ports
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set_driving_cell -lib_cell sky130_osu_sc_18T_ms__dff_1 -pin Q $all_in_ex_clk
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# Set input/output delay
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set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
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set_output_delay 0.0 -max -clock $my_clk [all_outputs]
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# Setting load constraint on output ports
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set_load [expr [load_of sky130_osu_sc_18T_ms_TT_1P8_25C.ccs/sky130_osu_sc_18T_ms__dff_1/D] * 1] [all_outputs]
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# Set the wire load model
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set_wire_load_mode "top"
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# Attempt Area Recovery - if looking for minimal area
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# set_max_area 2000
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# Set fanout
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set_max_fanout 6 $all_in_ex_clk
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# Fix hold time violations
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set_fix_hold [all_clocks]
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# Deal with constants and buffers to isolate ports
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set_fix_multiple_port_nets -all -buffer_constants
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# setting up the group paths to find out the required timings
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#group_path -name OUTPUTS -to [all_outputs]
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#group_path -name INPUTS -from [all_inputs]
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#group_path -name COMBO -from [all_inputs] -to [all_outputs]
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# Save Unmapped Design
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set filename [format "%s%s%s" "unmapped/" $my_toplevel ".ddc"]
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write_file -format ddc -hierarchy -o $filename
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# Compile statements - either compile or compile_ultra
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compile -scan -incr -map_effort low
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# compile_ultra -no_seq_output_inversion -no_boundary_optimization
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# Eliminate need for assign statements (yuck!)
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set verilogout_no_tri true
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set verilogout_equation false
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# setting to generate output files
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set write_v 1 ;# generates structual netlist
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set write_sdc 1 ;# generates synopsys design constraint file for p&r
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set write_ddc 1 ;# compiler file in ddc format
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set write_sdf 1 ;# sdf file for backannotated timing sim
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set write_pow 1 ;# genrates estimated power report
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set write_rep 1 ;# generates estimated area and timing report
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set write_cst 1 ;# generate report of constraints
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set write_hier 1 ;# generate hierarchy report
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# Report Constraint Violators
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set filename [format "%s%s%s" "reports/" $my_toplevel "_constraint_all_violators.rpt"]
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redirect $filename {report_constraint -all_violators}
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# Check design
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redirect reports/check_design.rpt { check_design }
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# Report Final Netlist (Hierarchical)
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set filename [format "%s%s%s" "mapped/" $my_toplevel ".vh"]
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write_file -f verilog -hierarchy -output $filename
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set filename [format "%s%s%s" "mapped/" $my_toplevel ".sdc"]
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write_sdc $filename
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set filename [format "%s%s%s" "mapped/" $my_toplevel ".ddc"]
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write_file -format ddc -hierarchy -o $filename
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set filename [format "%s%s%s" "mapped/" $my_toplevel ".sdf"]
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write_sdf $filename
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# QoR
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set filename [format "%s%s%s" "reports/" $my_toplevel "_qor.rep"]
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redirect $filename { report_qor }
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# Report Timing
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set filename [format "%s%s%s" "reports/" $my_toplevel "_reportpath.rep"]
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redirect $filename { report_path_group }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_report_clock.rep"]
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redirect $filename { report_clock }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_timing.rep"]
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redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_min_timing.rep"]
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redirect $filename { report_timing -delay min }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_area.rep"]
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redirect $filename { report_area -hierarchy -nosplit -physical -designware}
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set filename [format "%s%s%s" "reports/" $my_toplevel "_cell.rep"]
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redirect $filename { report_cell [get_cells -hier *] }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_power.rep"]
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redirect $filename { report_power }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_constraint.rep"]
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redirect $filename { report_constraint }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_hier.rep"]
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redirect $filename { report_hierarchy }
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# Quit
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quit
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184
synthDC/scripts/synth.tcl~
Executable file
184
synthDC/scripts/synth.tcl~
Executable file
@ -0,0 +1,184 @@
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#
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# Main Synopsys Flow
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# james.stine@okstate.edu 26 Jan 2022
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#
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# Config
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set hdl_src "../pipelined/src"
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eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {hdl/}
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eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {reports/}
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eval file copy [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
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eval file copy [glob ${hdl_src}/*/*.sv] {hdl/}
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eval file copy [glob ${hdl_src}/*/flop/*.sv] {hdl/}
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# Verilog files
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set my_verilog_files [glob hdl/*]
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# Set toplevel
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set my_toplevel wallypipelinedcore
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# Set number of significant digits
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set report_default_significant_digits 6
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# V(HDL) Unconnectoed Pins Output
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set verilogout_show_unconnected_pins "true"
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set vhdlout_show_unconnected_pins "true"
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#
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# Due to parameterized Verilog must use analyze/elaborate and not
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# read_verilog/vhdl (change to pull in Verilog and/or VHDL)
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#
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define_design_lib WORK -path ./WORK
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analyze -f sverilog -lib WORK $my_verilog_files
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#
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# Added if you had any VHDL
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# analyze -f vhdl -lib WORK $my_vhdl_files
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#
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elaborate $my_toplevel -lib WORK
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# Set the current_design
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current_design $my_toplevel
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link
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# Reset all constraints
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reset_design
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# Set Frequency in [MHz] or [ps]
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set my_clock_pin clk
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set my_clk_freq_MHz 25
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set my_period [expr 1000 / $my_clk_freq_MHz]
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set my_uncertainty [expr .1 * $my_period]
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# Create clock object
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set find_clock [ find port [list $my_clock_pin] ]
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if { $find_clock != [list] } {
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echo "Found clock!"
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set my_clk $my_clock_pin
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create_clock -period $my_period $my_clk
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set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
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} else {
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echo "Did not find clock! Design is probably combinational!"
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set my_clk vclk
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create_clock -period $my_period -name $my_clk
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}
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# Partitioning - flatten or hierarchically synthesize
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#ungroup -flatten -simple_names { dp* }
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#ungroup -flatten -simple_names { c* }
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#ungroup -all -flatten -simple_names
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# Set input pins except clock
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set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
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# Specifies delays be propagated through the clock network
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set_propagated_clock [get_clocks $my_clk]
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# Setting constraints on input ports
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set_driving_cell -lib_cell sky130_osu_sc_18T_ms__dff_1 -pin Q $all_in_ex_clk
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# Set input/output delay
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set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
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set_output_delay 0.0 -max -clock $my_clk [all_outputs]
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# Setting load constraint on output ports
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set_load [expr [load_of sky130_osu_sc_18T_ms_TT_1P8_25C.ccs/sky130_osu_sc_18T_ms__dff_1/D] * 1] [all_outputs]
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# Set the wire load model
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set_wire_load_mode "top"
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# Attempt Area Recovery - if looking for minimal area
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# set_max_area 2000
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# Set fanout
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set_max_fanout 6 $all_in_ex_clk
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# Fix hold time violations
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set_fix_hold [all_clocks]
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# Deal with constants and buffers to isolate ports
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set_fix_multiple_port_nets -all -buffer_constants
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# setting up the group paths to find out the required timings
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#group_path -name OUTPUTS -to [all_outputs]
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#group_path -name INPUTS -from [all_inputs]
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#group_path -name COMBO -from [all_inputs] -to [all_outputs]
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# Save Unmapped Design
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||||
set filename [format "%s%s%s" "unmapped/" $my_toplevel ".ddc"]
|
||||
write_file -format ddc -hierarchy -o $filename
|
||||
|
||||
# Compile statements - either compile or compile_ultra
|
||||
compile -scan -incr -map_effort high
|
||||
# compile_ultra -no_seq_output_inversion -no_boundary_optimization
|
||||
|
||||
# Eliminate need for assign statements (yuck!)
|
||||
set verilogout_no_tri true
|
||||
set verilogout_equation false
|
||||
|
||||
# setting to generate output files
|
||||
set write_v 1 ;# generates structual netlist
|
||||
set write_sdc 1 ;# generates synopsys design constraint file for p&r
|
||||
set write_ddc 1 ;# compiler file in ddc format
|
||||
set write_sdf 1 ;# sdf file for backannotated timing sim
|
||||
set write_pow 1 ;# genrates estimated power report
|
||||
set write_rep 1 ;# generates estimated area and timing report
|
||||
set write_cst 1 ;# generate report of constraints
|
||||
set write_hier 1 ;# generate hierarchy report
|
||||
|
||||
# Report Constraint Violators
|
||||
set filename [format "%s%s%s" "reports/" $my_toplevel "_constraint_all_violators.rpt"]
|
||||
redirect $filename {report_constraint -all_violators}
|
||||
|
||||
# Check design
|
||||
redirect reports/check_design.rpt { check_design }
|
||||
|
||||
# Report Final Netlist (Hierarchical)
|
||||
set filename [format "%s%s%s" "mapped/" $my_toplevel ".vh"]
|
||||
write_file -f verilog -hierarchy -output $filename
|
||||
|
||||
set filename [format "%s%s%s" "mapped/" $my_toplevel ".sdc"]
|
||||
write_sdc $filename
|
||||
|
||||
set filename [format "%s%s%s" "mapped/" $my_toplevel ".ddc"]
|
||||
write_file -format ddc -hierarchy -o $filename
|
||||
|
||||
set filename [format "%s%s%s" "mapped/" $my_toplevel ".sdf"]
|
||||
write_sdf $filename
|
||||
|
||||
# QoR
|
||||
set filename [format "%s%s%s" "reports/" $my_toplevel "_qor.rep"]
|
||||
redirect $filename { report_qor }
|
||||
|
||||
# Report Timing
|
||||
set filename [format "%s%s%s" "reports/" $my_toplevel "_reportpath.rep"]
|
||||
redirect $filename { report_path_group }
|
||||
|
||||
set filename [format "%s%s%s" "reports/" $my_toplevel "_report_clock.rep"]
|
||||
redirect $filename { report_clock }
|
||||
|
||||
set filename [format "%s%s%s" "reports/" $my_toplevel "_timing.rep"]
|
||||
redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 }
|
||||
|
||||
set filename [format "%s%s%s" "reports/" $my_toplevel "_min_timing.rep"]
|
||||
redirect $filename { report_timing -delay min }
|
||||
|
||||
set filename [format "%s%s%s" "reports/" $my_toplevel "_area.rep"]
|
||||
redirect $filename { report_area -hierarchy -nosplit -physical -designware}
|
||||
|
||||
set filename [format "%s%s%s" "reports/" $my_toplevel "_cell.rep"]
|
||||
redirect $filename { report_cell [get_cells -hier *] }
|
||||
|
||||
set filename [format "%s%s%s" "reports/" $my_toplevel "_power.rep"]
|
||||
redirect $filename { report_power }
|
||||
|
||||
set filename [format "%s%s%s" "reports/" $my_toplevel "_constraint.rep"]
|
||||
redirect $filename { report_constraint }
|
||||
|
||||
set filename [format "%s%s%s" "reports/" $my_toplevel "_hier.rep"]
|
||||
redirect $filename { report_hierarchy }
|
||||
|
||||
# Quit
|
||||
quit
|
||||
|
||||
Loading…
Reference in New Issue
Block a user