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Author SHA1 Message Date
Harshini Srinath
6b5aa47f23
Fixed formatting 2023-07-30 17:54:47 -07:00
Harshini Srinath
8c7ea5a47a
Fixed formatting 2023-07-30 17:46:23 -07:00
Harshini Srinath
69711503a8
Fixed formatting 2023-07-30 17:39:37 -07:00
Harshini Srinath
70599d3153
Fixed formatting 2023-07-30 17:38:22 -07:00
Harshini Srinath
2846a2f567
Fixed spacing 2023-07-30 17:32:46 -07:00
Harshini Srinath
fffde4ef7d
Fixed spacing 2023-07-30 17:22:40 -07:00
Harshini Srinath
31c09cf3cf
Fixed spacing 2023-07-30 17:21:52 -07:00
Harshini Srinath
c49944a495
Fixed spacing 2023-07-30 17:21:22 -07:00
Harshini Srinath
84d72bc203
Fixed spacing 2023-07-30 17:18:25 -07:00
Harshini Srinath
b8570c4bef
Fixed spacing 2023-07-30 16:59:27 -07:00
Harshini Srinath
872f9ed9cc
Fixed spacing 2023-07-30 16:57:57 -07:00
harshinisrinath
15dbbef9ad Fixed bug and tried to reset menvcfg to improve testing of csri in priv. 2023-07-30 16:40:06 -07:00
David Harris
f7f4c5fa7b renamed test-shared.vh to config-shared.vh 2023-07-30 05:22:39 -07:00
David Harris
388d699baa Cleaned up lint for plic_apb part select 2023-07-30 02:00:38 -07:00
David Harris
54d6a1afa2 Fixed Questa warnings in plic_apb about part select out of bounds 2023-07-30 01:54:41 -07:00
Jacob Pease
6c8bbf7f13 Merge branch 'main' of github.com:openhwgroup/cvw 2023-07-28 12:49:19 -05:00
David Harris
5fa84ddac4
Merge pull request #371 from ross144/main 
Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv.  STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop.
 2023-07-28 09:51:58 -07:00
Ross Thompson
84600937c8 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-28 11:23:17 -05:00
Ross Thompson
8d88ef93bc Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop. 2023-07-28 11:20:29 -05:00
Jacob Pease
d3476b64cd Updated VCU108 device tree for 256MB memory. 2023-07-27 17:44:31 -05:00
Ross Thompson
e4327d3489
Merge pull request #370 from JacobPease/main 
Fixed GPIO pin names in fpgaTop.v
 2023-07-27 16:10:44 -04:00
Jacob Pease
87a6ad5a87 Removed non-existent SDC dependency from VCU targets in FPGA Makefile. 2023-07-27 15:01:20 -05:00
Jacob Pease
f696cf9955 Merge branch 'main' of github.com:openhwgroup/cvw 2023-07-27 14:46:01 -05:00
David Harris
746891eac5
Merge pull request #369 from ross144/main 
Fixed issue #368 lint, but not simulation
 2023-07-26 13:32:02 -07:00
Ross Thompson
52dc71507f Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN. 2023-07-26 15:08:01 -05:00
Jacob Pease
8b97d323e0 Fixed GPIO pin names in fpgaTop.v 2023-07-25 20:57:04 -05:00
David Harris
6e0d5d9962
Merge pull request #367 from ross144/main 
Complete removal of old flash card hardware and updates to Arty A7 to push clock speed to 20Mhz and increase memory to 256 MiB
 2023-07-25 15:26:08 -07:00
Ross Thompson
1b8edacd8d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-25 15:13:07 -05:00
Ross Thompson
8dc7870e62 Updated Arty A7 fpga config and device tree to 256MiB main memory. 2023-07-25 15:11:47 -05:00
Ross Thompson
97540791de
Merge pull request #366 from davidharrishmc/dev 
Progress toward DC synthesis
 2023-07-25 11:39:49 -04:00
David Harris
0cfb5c7b3a Formatting cleanup 2023-07-25 05:11:38 -07:00
David Harris
f2623a7229 Progress toward synthesis with parameterized design 2023-07-25 05:10:53 -07:00
Ross Thompson
a543aa2b71 Removed old sdc from all configs. 2023-07-24 15:55:22 -05:00
Ross Thompson
717833b11a Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00
David Harris
89332c35f2 Fixed synthesis Makefile to match new configuration 2023-07-24 11:32:46 -07:00
Ross Thompson
d418e4fa5e Updated arty a7 device clock speed for 20Mhz. 2023-07-24 11:50:00 -05:00
Ross Thompson
fd187e9ee6 Merge branch 'main' of github.com:ross144/cvw 2023-07-24 10:47:05 -05:00
Ross Thompson
d239b0649e Improved timing constraints for arty a7 to push clock speed to 20Mhz. 2023-07-24 10:46:49 -05:00
harshinisrinath
24792d82e9 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-07-23 11:59:43 -07:00
David Harris
1f54c82cdd
Merge pull request #364 from ross144/main 
Updated to the newest vivado and required removing the paramized enum. Also includes Jacob's SD card updates and new boot process.
 2023-07-22 18:52:24 -07:00
Ross Thompson
6099b0e763 Fixed bugs in boot and new flash card merge. Works with arty a7 now. 2023-07-22 15:52:25 -05:00
Ross Thompson
608400ac6a Updated arty a7 device tree. 2023-07-21 19:08:45 -05:00
Ross Thompson
6e17cfba03 At least it simulates and gets through fpga elaboration. 2023-07-21 18:40:26 -05:00
Ross Thompson
3eeecd2f27 Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
0063665baf Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now. 2023-07-21 16:31:26 -05:00
Ross Thompson
a3efddd60b
Merge pull request #365 from JacobPease/boot 
Boot
Jacob's account is passing the ECA, but there are some old commits from Jan on James Stine's account which are already in the repo which were merged into this pull request which appear as anonymous users. I don't think it's possible to fix this without a significant headache.  We'd have to cherry-pick each of Jacob's 21 commits.  I'm planning to merge his work into main today/weekend and this will make the job harder. Since these commits are already part of main I'm going to merge this.
 2023-07-21 17:26:41 -04:00
Ross Thompson
37078f3d9b Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
Jacob Pease
36785848a5 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Ross Thompson
7873d26678 Fixed a bunch of timing constraints for the arty a7 board. 2023-07-19 17:08:16 -05:00
Ross Thompson
9ba3113e9c Improved critical path. 2023-07-19 14:59:37 -05:00