529 Commits

Author	SHA1	Message	Date
Katherine Parry	9eb6eb40bf	rv64f FLW passes imperas tests	2021-06-22 16:36:16 -04:00
Kip Macsai-Goren	d6c5c61b59	Fixed mask assignment error, made usage, variables more clear	2021-06-22 13:31:06 -04:00
Kip Macsai-Goren	b78c09baed	Continued fixing fsm to work right with svmode	2021-06-22 13:29:49 -04:00
Kip Macsai-Goren	852bb9296f	updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop	2021-06-22 11:21:11 -04:00
David Harris	29ad38fb9e	Added Physical Address and Size to PMA Checker/MMU	2021-06-21 01:27:02 -04:00
David Harris	aef408af58	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
David Harris	0a59b006ab	Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals	2021-06-20 22:59:04 -04:00
bbracker	83a1f29c37	remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR	2021-06-20 22:38:25 -04:00
Katherine Parry	26bad083ad	all rv64f instructions except convert, divide, square root, and FLD pass	2021-06-20 20:24:09 -04:00
bbracker	7aa2f0d953	make xCOUNTEREN what buildroot expects it to be	2021-06-20 09:22:31 -04:00
Ross Thompson	bb756849a7	Revert "Icache now uses physical lenght bits rather than XLEN." ... This reverts commit d4de8a54a2.	2021-06-19 08:58:34 -05:00
Ross Thompson	e4c932265d	Revert "Improved some names in icache." ... This reverts commit 22ea801edb.	2021-06-19 08:58:32 -05:00
Ross Thompson	22ea801edb	Improved some names in icache.	2021-06-18 12:22:41 -05:00
Ross Thompson	d4de8a54a2	Icache now uses physical lenght bits rather than XLEN.	2021-06-18 12:02:59 -05:00
David Harris	21a55458ca	Made MemPAdrM and related signals PA_BITS wide	2021-06-18 09:36:22 -04:00
David Harris	a3f3533cce	Changed physical addresses to PA_BITS in size in MMU and TLB	2021-06-18 09:11:31 -04:00
David Harris	cc78504ae4	Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX	2021-06-18 08:13:15 -04:00
David Harris	72d8d34e3c	allow all size memory access in CLINT; added underscore to peripheral address symbols	2021-06-18 08:05:50 -04:00
David Harris	e03912f64c	Cleaned up name of MTIME register in CSRC	2021-06-18 07:53:49 -04:00
David Harris	8357b14957	Further cleaning of PMA checker	2021-06-17 22:27:39 -04:00
David Harris	91a13999a9	Added SUPPORTED to each peripheral in each config file	2021-06-17 21:36:32 -04:00
David Harris	5e7ed4bd88	added inputs to pmaadrdec	2021-06-17 18:54:39 -04:00
David Harris	09c5e27853	Started simplifying PMA checker	2021-06-17 16:28:06 -04:00
bbracker	076469230f	added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version	2021-06-17 12:09:10 -04:00
bbracker	db0abfd36d	enable TIME CSR for 32 bit mode as well	2021-06-17 11:34:16 -04:00
bbracker	7d1469a06c	provide time and timeh CSRs based on CLINT's counter	2021-06-17 08:38:30 -04:00
bbracker	0647094e73	PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable	2021-06-17 05:19:36 -04:00
bbracker	7a652139b5	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
bbracker	6f1f585c2c	Merge remote-tracking branch 'origin/fixPrivTests' into main	2021-06-15 09:57:46 -04:00
Katherine Parry	920ff984ca	Updated FMA	2021-06-14 13:42:53 -04:00
David Harris	5e01f71c52	disabled Verilator WIDTH warnings in ICCacheCntrl	2021-06-12 19:50:06 -04:00
Ross Thompson	5d7ca87982	fixed the mtime register.	2021-06-11 13:50:13 -05:00
James E. Stine	171a6728b0	Put repository of fpdivsqrt with RTL-based adder instead of structural implementation	2021-06-11 14:35:22 -04:00
David Harris	79ee817d91	Reverted MIDELEG and MEDELEG to XLEN so busybear passes	2021-06-10 23:47:32 -04:00
David Harris	690e2b7f31	Restored counter events	2021-06-10 11:18:58 -04:00
David Harris	0e4e091a39	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-10 10:47:55 -04:00
David Harris	c3d106f0f0	Removed two cycles of latency from the DTIM	2021-06-10 10:30:24 -04:00
bbracker	9c3cb0d2bf	peripheral lint fixes	2021-06-10 10:19:10 -04:00
bbracker	f0266f621b	merge	2021-06-10 10:03:01 -04:00
bbracker	58d0e46d02	UART improved and added more reg read side effects	2021-06-10 09:53:48 -04:00
David Harris	17b76d4cd7	Configurable number of performance counters	2021-06-10 09:41:26 -04:00
David Harris	6dcf86948c	Restored PCCorrectE declaration in IFU	2021-06-09 21:09:16 -04:00
David Harris	e231fc6b00	More verilator fixes, but bpred is broken	2021-06-09 21:03:03 -04:00
David Harris	9dd3857c26	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
David Harris	9a17556de4	Start to parameterize number of PMP Entries	2021-06-08 15:29:22 -04:00
David Harris	cfe5c27946	Resized BOOT TIM to 1 KB	2021-06-08 14:04:32 -04:00
Kip Macsai-Goren	6ed96761b6	Merge small mmu changes into main	2021-06-08 14:00:26 -04:00
Kip Macsai-Goren	be99c18002	making mmu branch line up with main	2021-06-08 13:59:03 -04:00
Kip Macsai-Goren	41ceb20296	some cleanup of signals, not done yet	2021-06-08 13:39:32 -04:00
bbracker	17960a6484	Ah big ole merge! Passes sim-wally-batch and linting, so should be fine	2021-06-08 12:41:25 -04:00