Ross Thompson
9bcb105aa4
Changed names of Icache signals.
2021-12-30 11:01:11 -06:00
Ross Thompson
a37c7515bd
Icache now works with any sized cache line a power of 2, greater than or equal to 32.
2021-12-30 10:37:57 -06:00
Ross Thompson
d50a65720d
More name cleanup in caches.
2021-12-30 09:18:16 -06:00
Ross Thompson
d474caf24f
Removed WAdr from cacheway as it is redundant.
2021-12-29 21:39:43 -06:00
Ross Thompson
050523487c
Changed names of lsu address signals.
2021-12-29 15:03:34 -06:00
Ross Thompson
79b17c5b55
Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
2021-12-28 12:33:07 -06:00
Ross Thompson
a445bedcd2
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
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This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
2021-12-19 14:57:42 -06:00
Ross Thompson
6d2a4b8354
Oups missed files in the last commit.
2021-12-15 10:25:08 -06:00
Ross Thompson
705572f0ac
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
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If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
Ross Thompson
8a51fe76c1
Partial cleanup of unused signals in caches and bpred.
2021-10-24 15:04:20 -05:00
David Harris
c9e9cd4a60
more lsu/ifu lint cleanup
2021-10-23 12:10:13 -07:00
David Harris
2cfbd888fd
more lsu/ifu lint cleanup
2021-10-23 12:00:32 -07:00
Ross Thompson
0b1e59d075
Updated Dcache to fully support flush. This appears to work.
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Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
2021-09-17 10:25:21 -05:00
Ross Thompson
615fd41e7b
Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
2021-09-16 18:32:29 -05:00
Ross Thompson
d901f60a6d
Added flush controls to cachway.
2021-09-16 16:56:48 -05:00
Ross Thompson
cae350abb7
Added invalidate to icache.
2021-09-16 16:15:54 -05:00
Ross Thompson
6f4542f063
Third attempt at fixing the write enables for the icache cacheway.
2021-09-09 15:08:10 -05:00
Ross Thompson
1d370ca71f
fixed some lint bugs.
2021-09-09 12:38:57 -05:00
Ross Thompson
49e75d579c
Set associate icache working, but way 0 is never written.
2021-09-07 12:46:16 -05:00
Ross Thompson
05455f8392
Changed name of memory in icache.
2021-09-06 20:54:52 -05:00
Ross Thompson
2968623f9a
Partial multiway set associative icache.
2021-08-30 10:49:24 -05:00
Ross Thompson
d433db3048
Renamed PCMux (icache) to SelAdr to match dcache.
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Removed unused cache files.
2021-08-27 11:14:10 -05:00
Ross Thompson
96cbd8e785
Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm.
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One downside is it increases the icache complexity. However it also fixes an untested bug. If a region
was uncacheable it would have been possible for the request to be made multiple times. Now that is
not possible. Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
2021-08-27 11:03:36 -05:00
Ross Thompson
4ace7fe946
Renamed ICacheCntrl to icachefsm.
2021-08-26 15:57:17 -05:00
Ross Thompson
d6ff89b7e6
Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits.
2021-08-26 15:43:02 -05:00
Ross Thompson
aea7afead6
Finished moving data path logic from the ICacheCntrl.sv to icache.sv.
2021-08-26 13:06:24 -05:00
Ross Thompson
86fc632790
Moved data path logic from icacheCntrl to icache.
2021-08-26 10:58:19 -05:00
Ross Thompson
e4bbd3bbc7
Converted the icache type from logic to state type.
2021-08-26 10:41:42 -05:00
David Harris
e1a1a8395e
Parameterized I$/D$ configurations and added sanity check assertions in testbench
2021-07-20 08:57:13 -04:00
Ross Thompson
118dfa9cec
added page table walker fault exit for icache.
2021-07-01 17:59:55 -05:00
Ross Thompson
dd84f2958e
Page table walker now walks the table.
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Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Ross Thompson
f74ecbb81e
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
Ross Thompson
f79e5eaa47
Icache now uses physical lenght bits rather than XLEN.
2021-06-21 16:41:09 -05:00
Ross Thompson
70c45a5349
Revert "Icache now uses physical lenght bits rather than XLEN."
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This reverts commit 16266d978a
2021-06-19 08:58:34 -05:00
Ross Thompson
16266d978a
Icache now uses physical lenght bits rather than XLEN.
2021-06-18 12:02:59 -05:00
Ross Thompson
191f7e61fd
Moved I-Cache offset selection mux to icache.sv (top level).
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When we switch to set associative this is will be more efficient.
2021-06-04 13:49:33 -05:00
Ross Thompson
fdef8df76b
Reorganized the icache names.
2021-06-04 12:53:42 -05:00
Ross Thompson
7c44f19925
Relocated the icache to the cache directoy.
2021-06-04 12:23:46 -05:00
