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Author SHA1 Message Date
David Harris
9b7f385c50 Temporary fix of InstrM to prevent testbench hanging 2023-11-03 04:59:44 -07:00
David Harris
409ecc53bd Fixed regression error of watchdog timeout when PCM is optimized out of the IFU 2023-11-03 04:38:27 -07:00
Rose Thompson
92d4d7626c
Merge pull request #449 from davidharrishmc/dev 
Synthesis cleanup
 2023-11-02 12:26:55 -05:00
David Harris
c99d29cf95 Removed .gitattributes 2023-11-01 17:50:44 -07:00
David Harris
c639f92d27 Improved comments about memory read paths 2023-11-01 07:00:17 -07:00
David Harris
6f021aac54 Fixes to config extraction 2023-10-31 06:27:55 -07:00
David Harris
bd6e189680 130 nm synthesis script improvements 2023-10-30 20:57:35 -07:00
David Harris
d2ccba9a49 Conditionally instantiate hardware in ifu 2023-10-30 20:55:00 -07:00
David Harris
d0735887de Gated InstrOrigM and PCMReg when not needed 2023-10-30 20:05:37 -07:00
David Harris
4bd830e578 rom1p1r code cleanup 2023-10-30 19:47:49 -07:00
David Harris
7b3dcdc262 rom1p1r code cleanup 2023-10-30 19:46:38 -07:00
David Harris
c472f4dc3c Made 2-bit AdrReg conditional on being needed 2023-10-30 19:13:43 -07:00
Rose Thompson
e3f769a563
Merge pull request #445 from davidharrishmc/dev 
Fix issue 444; no delegating misaligned instructions if they can't happen
 2023-10-30 12:25:42 -05:00
David Harris
4d191e63cc Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder. 2023-10-30 09:56:17 -07:00
David Harris
12d1aed8a9 Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported. 2023-10-30 07:06:34 -07:00
Rose Thompson
77e6ac487a
Merge pull request #443 from davidharrishmc/dev 
Wrapper synthesis fix.
 2023-10-27 09:25:06 -05:00
David Harris
5ca5443835 Fixed reporting of timing on modules with wrappers 2023-10-26 20:14:14 -07:00
David Harris
d5d196b870 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-10-26 19:02:05 -07:00
David Harris
b1796daca7
Merge pull request #441 from ross144/main 
Fixed issues #200
 2023-10-26 10:26:58 -07:00
Rose Thompson
9ca3bfc2c8 Updated comments about Interrupt and wfi. 2023-10-26 12:24:36 -05:00
Rose Thompson
63bcc7655c Forgot to include this file in the last commit. 2023-10-26 12:20:42 -05:00
Rose Thompson
4c4103dfe8 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-26 12:15:22 -05:00
Rose Thompson
dd9059317f Cleaned up the implementation changes for wfi. 2023-10-24 23:11:48 -05:00
Rose Thompson
e4aebbaaa5 This version passes the regression test and solves issue #200. wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps. 2023-10-24 22:58:26 -05:00
Rose Thompson
bc877e9ca7 Possible fix for wfi. 2023-10-24 18:08:33 -05:00
David Harris
17fd0c90da Fixed warnings of signed conversion and for Design Compiler 2023-10-24 14:01:43 -07:00
David Harris
7fc5268f47 Tested assembly language file for the pause example 2023-10-24 10:45:41 -07:00
David Harris
de52710a60
Merge pull request #439 from ross144/main 
Fixes to branch predictor processing scripts.
 2023-10-24 08:31:06 -07:00
Rose Thompson
25a3a2f33b Fixed bug in bpred-sim.py for btb and class size sweep. 2023-10-24 10:29:02 -05:00
Rose Thompson
bad9afc012 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-23 16:14:30 -05:00
Rose Thompson
c296bd3a02 Updated bpred-sim.py to take command line options to select between sweeping direction, target, class, or ras prediction. 2023-10-23 16:09:40 -05:00
Rose Thompson
bce15ce367 Added support for branch counters when there is no branch predictor. 2023-10-23 15:32:03 -05:00
Rose Thompson
2b031ea445 Fixed issue 250. instruction classification was not correct for jalr ra (non zero). 2023-10-23 15:30:43 -05:00
Rose Thompson
7347ed2527 Addeed script to sweep sim_bp for btb. 2023-10-23 15:29:50 -05:00
David Harris
deebc84084
Merge pull request #438 from ross144/main 
Fixed comments in cboz and cbom tests.
 2023-10-20 17:15:59 -07:00
Rose Thompson
e3154bb7a3 Updated comments in the cboz tests. 2023-10-20 15:15:47 -05:00
Rose Thompson
74574f96cf Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-20 15:14:02 -05:00
Rose Thompson
badfc1e4bb Updated comments for the cbom tests. 2023-10-20 15:13:52 -05:00
Rose Thompson
99671ebbcd
Merge pull request #437 from davidharrishmc/dev 
synth improvements
 2023-10-19 16:23:34 -05:00
David Harris
46d16305a4 Set drive for Sky130 2023-10-19 13:46:30 -07:00
David Harris
aa3bc10259 Modified log2 coding to avoid synthesis warning 2023-10-19 11:16:02 -07:00
Rose Thompson
c5de241436
Merge pull request #436 from davidharrishmc/dev 
Automatic generation of synthesis wrappers when needed
 2023-10-19 12:51:24 -05:00
David Harris
b28777fae0 Removed wrapper from wallySynth because it is automatic now 2023-10-19 10:49:06 -07:00
David Harris
8c6b17de6d Updated wrapper generation to be automatic without specifying WRAPPER=1; instead looks for cvw_t in the file. Also starting to add OSU 130 nm synthesis. 2023-10-19 10:44:03 -07:00
David Harris
379337fee0 Adjusted synthesis scripts to report on DESIGN even when a wrapper is used 2023-10-19 06:16:52 -07:00
Rose Thompson
ba6785d04f
Merge pull request #434 from davidharrishmc/dev 
Config and peripheral cleanup
 2023-10-18 17:58:29 -05:00
David Harris
054d9ed38c Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-10-18 14:40:19 -07:00
David Harris
46b1ff00d6
Merge pull request #435 from kipmacsaigoren/synth_wrapper_gen 
synth wrapper generation bug fix
 2023-10-18 14:34:37 -07:00
Kevin Kim
0a15466f21 wrapper bug fix 2023-10-18 14:29:46 -07:00
David Harris
09b3a49471 Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates 2023-10-18 05:50:41 -07:00