Github_Repos/cvw
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4,293 Commits 5 Branches 2 Tags 53 MiB
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58 Commits

Author SHA1 Message Date
David Harris
c3122ce214 sram1rw cleanup 2022-02-03 18:03:22 +00:00
Ross Thompson
23c4ba2777 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. 
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
 2022-01-26 18:23:39 -06:00
David Harris
3d2671a8b0 Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
Ross Thompson
e0740034f0 Clean up of cachefsm. 2022-01-06 16:32:49 -06:00
Ross Thompson
a4afc1bc54 More name cleanup in cache. 2022-01-05 22:37:53 -06:00
Ross Thompson
da585b30f9 Slower but correct implementation of flush. 2022-01-05 16:57:22 -06:00
Ross Thompson
cc51a27a34 Fixed bug with flush dirty not cleared in the correct cache line. 2022-01-05 14:14:01 -06:00
Ross Thompson
98be8201b2 Renamed most signals inside cache.sv so they are agnostic to i or d. 2022-01-04 23:52:42 -06:00