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1,425 Commits 6 Branches 2 Tags 53 MiB
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46 Commits

Author SHA1 Message Date
David Harris
f806707cb0 Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram 2021-07-08 16:58:11 -04:00
David Harris
b1592a0542 TLB cleanup to match diagrams 2021-07-08 16:52:06 -04:00
David Harris
6dc49dd073 Renamed tlb ReadLines to Matches 2021-07-07 06:32:26 -04:00
David Harris
2b26bbbbd7 more TLB name touchups 2021-07-06 18:39:30 -04:00
David Harris
73024fee2d connected signals in tlb by name instead of .* 2021-07-06 17:22:10 -04:00
David Harris
18f4fa600a changed tlbphysicalpagemask to structural 2021-07-06 17:16:58 -04:00
David Harris
78850bfcd8 MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB 2021-07-06 15:29:42 -04:00
David Harris
4c2cbe3200 Cleaned up tlb output muxing 2021-07-06 10:44:05 -04:00
David Harris
087bed3b67 Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines 2021-07-06 10:38:30 -04:00
David Harris
69c0358ffd Created tlbcontrol module to hide details 2021-07-06 03:25:11 -04:00
David Harris
cc04009f82 Touched up TLB D and A bit checks 2021-07-04 18:17:09 -04:00
David Harris
595df47a3e Fixed TLB_ENTRIES merge conflict and handling of global PTEs 2021-07-04 18:05:22 -04:00
David Harris
6b9cfe90d8 Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:52:00 -04:00
David Harris
b59213c83f Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders 2021-07-04 16:33:13 -04:00
David Harris
deae60eb1d TLB cleanup 2021-07-04 14:59:04 -04:00
David Harris
243c03f870 TLB cleanup 2021-07-04 14:37:53 -04:00
David Harris
fed096407b TLB minor organization 2021-07-04 14:30:56 -04:00
David Harris
a5c0dc8c81 Fixed MPRV and MXR checks in TLB 2021-07-04 13:20:29 -04:00
David Harris
5b891e05ac TLB mux and swizzling cleanup 2021-07-04 12:53:52 -04:00
David Harris
622060b99f Replaced generates with arrays in TLB 2021-07-04 12:32:27 -04:00
Ross Thompson
ae6140bd94 Don't use this branch walker still broken. 2021-06-28 17:26:11 -05:00
Ross Thompson
6134c22aca Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two. 
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
 2021-06-23 16:43:22 -05:00
David Harris
a3f3533cce Changed physical addresses to PA_BITS in size in MMU and TLB 2021-06-18 09:11:31 -04:00
Kip Macsai-Goren
be99c18002 making mmu branch line up with main 2021-06-08 13:59:03 -04:00
Kip Macsai-Goren
41ceb20296 some cleanup of signals, not done yet 2021-06-08 13:39:32 -04:00
Kip Macsai-Goren
e044f72e59 remove redundant decodes, fixed mmu logic ins/outs 2021-06-07 19:23:30 -04:00
Kip Macsai-Goren
146ed95bdb got rid of some underscores in filenames, modules 2021-06-07 18:54:05 -04:00
Kip Macsai-Goren
46b2b19792 implemented simpler page mixers, cleaned up a bit 2021-06-07 18:32:34 -04:00
David Harris
1e67db2f0c Second attept to commit refactoring config files 2021-06-07 12:37:46 -04:00
Kip Macsai-Goren
7e41b17e65 restructured so that pma/pmp are a part of mmu 2021-06-04 17:05:07 -04:00
Kip Macsai-Goren
f7deda0514 implemented Sv48. 2021-06-01 17:50:37 -04:00
Thomas Fleming
980c00fa64 Clean up MMU code 2021-05-14 07:12:32 -04:00
Thomas Fleming
70c801331a Implement virtual memory protection 2021-04-21 19:58:36 -04:00
Thomas Fleming
ae888b5705 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/pagetablewalker.sv
 2021-04-13 13:42:03 -04:00
Thomas Fleming
08a84048b6 Add lru algorithm to TLB 2021-04-13 13:37:24 -04:00
Teo Ene
0bffac2c74 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Thomas Fleming
bd310a55af Refactor TLB into multiple files 2021-04-08 03:24:10 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
Thomas Fleming
e04ad8f304 Fix extraneous page fault stall 2021-04-03 21:28:24 -04:00
Thomas Fleming
f9bf2fbc01 Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Thomas Fleming
9388a9f28a Disable 'always-on' virtual memory 2021-03-30 22:49:47 -04:00
Thomas Fleming
4b2765f8e2 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
062c4d40da Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Thomas Fleming
85dcbee86b Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Thomas Fleming
1a2db17ee5 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Thomas Fleming
7a9f866120 Move tlb into mmu directory 2021-03-04 02:39:08 -05:00