Ross Thompson
|
f643b45b97
|
Added branch outcome logger to testbench
|
2023-01-07 13:16:57 -06:00 |
|
Ross Thompson
|
48cf8d58b4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2023-01-06 15:18:13 -06:00 |
|
Ross Thompson
|
81fe08192e
|
Added python script to post process performance counter metrics.
|
2023-01-06 15:15:54 -06:00 |
|
Ross Thompson
|
cd17d296d2
|
Added code to print out performance counters at end of each test.
|
2023-01-05 18:00:11 -06:00 |
|
Ross Thompson
|
f8c656f1e0
|
Simiplified global history branch predictor.
|
2023-01-04 23:41:55 -06:00 |
|
Katherine Parry
|
fd3b967496
|
some commenting fixes, converter optimizations, and moves normshift into postproc
|
2023-01-03 15:55:30 -06:00 |
|
Katherine Parry
|
668c698bb4
|
removed ethe second bit from fma alignment shift
|
2022-12-30 12:07:44 -06:00 |
|
Katherine Parry
|
8150305919
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-12-30 09:56:35 -06:00 |
|
David Harris
|
18f19ce44d
|
fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression
|
2022-12-30 06:40:25 -08:00 |
|
Katherine Parry
|
e5a76817df
|
minor optimizations and renaming
|
2022-12-29 15:54:17 -06:00 |
|
Katherine Parry
|
b469831b53
|
one bitt removed from inital lignment shift
|
2022-12-28 17:46:53 -06:00 |
|
Cedar Turek
|
6d933a88c7
|
idiv passing radix 2, four copies
|
2022-12-27 22:10:48 -08:00 |
|
David Harris
|
0a0ca0ae07
|
cleanup
|
2022-12-27 21:29:36 -08:00 |
|
David Harris
|
d6aad0f3c3
|
Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M
|
2022-12-27 21:24:38 -08:00 |
|
David Harris
|
71f214df20
|
Moved fdivsqrtexpcalc to its own file
|
2022-12-26 08:45:43 -08:00 |
|
David Harris
|
0a067d342f
|
Restored missing floating point load/store tests
|
2022-12-25 22:28:14 -08:00 |
|
Katherine Parry
|
66510f38af
|
reworked negitive sticky bit handeling in fma
|
2022-12-23 17:01:34 -06:00 |
|
Ross Thompson
|
b6b30533e8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-22 22:51:33 -06:00 |
|
Ross Thompson
|
942acb354e
|
Closing in on icache flushed by FlushD rather than TrapM.
|
2022-12-22 20:19:09 -06:00 |
|
Kip Macsai-Goren
|
d25d699800
|
Added status.tvm bit test that passes make and regression
|
2022-12-22 14:43:22 -08:00 |
|
David Harris
|
a5dc09c97f
|
Added assertion about atomics needing caches
|
2022-12-21 13:57:28 -08:00 |
|
Ross Thompson
|
a6ffb4cef3
|
Added timeout check to testbench.
A watchdog checks the value of PCW. If it does not change within 1M cycles immediately stop simulation and report an error.
|
2022-12-21 09:18:00 -06:00 |
|
Ross Thompson
|
7a352edf13
|
Attempted to make a cache test.
|
2022-12-18 17:15:08 -06:00 |
|
Ross Thompson
|
9d1cb9337e
|
Updated tests for fpga and BP.
|
2022-12-18 16:24:26 -06:00 |
|
David Harris
|
3bef12b108
|
Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
|
2022-12-15 08:23:34 -08:00 |
|
cturek
|
930fcbe956
|
Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs
|
2022-12-10 21:56:35 +00:00 |
|
Kip Macsai-Goren
|
055ca9ee37
|
Addded fix for 32 bit periph test and added test to regression
|
2022-12-06 09:56:08 -08:00 |
|
Kip Macsai-Goren
|
55627f40e2
|
added passing GPIO test to 64 bit tests
|
2022-12-05 21:31:00 -08:00 |
|
Kip Macsai-Goren
|
c6662933c4
|
commented out periph test from wally32 periph so rv32ic doesn't hang
|
2022-12-05 20:23:16 -08:00 |
|
Kip Macsai-Goren
|
4e2f4855e6
|
added passing tests to regression
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
540d6c2f41
|
added -01 to all WALLY tests
|
2022-12-05 20:16:02 -08:00 |
|
Ross Thompson
|
fc05e27416
|
Updated riscv arch test removed misaligned1.
|
2022-12-04 00:18:10 +00:00 |
|
Ross Thompson
|
350fdd944d
|
Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."
This reverts commit fb221d7b64.
|
2022-12-04 00:01:58 +00:00 |
|
cturek
|
fb221d7b64
|
Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.
|
2022-12-02 21:44:29 +00:00 |
|
David Harris
|
db5f3c15a4
|
FPU divider working with execute stage stall
|
2022-12-02 11:11:53 -08:00 |
|
David Harris
|
6079a01bc8
|
update test list
|
2022-12-02 04:28:47 -08:00 |
|
David Harris
|
0d23ab3ec1
|
reorder tests
|
2022-12-01 16:27:33 -08:00 |
|
David Harris
|
3a8602523e
|
FPU test list
|
2022-12-01 10:18:36 -08:00 |
|
Ross Thompson
|
2f582cd91f
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-30 13:30:37 -06:00 |
|
Ross Thompson
|
cedb234013
|
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
|
2022-11-30 11:01:25 -06:00 |
|
Ross Thompson
|
0454eb95ad
|
Preparing to merge dirty and tag srams.
|
2022-11-30 10:40:48 -06:00 |
|
Ross Thompson
|
de538d1c2f
|
Intermediate commit. Replaced flip flop dirty bit array with sram.
|
2022-11-30 00:08:31 -06:00 |
|
cturek
|
10c2d45888
|
div tests in sim-wally
|
2022-11-30 02:32:04 +00:00 |
|
Kip Macsai-Goren
|
44ea8d8b22
|
added failing satp invalid tests to regression
|
2022-11-29 10:43:38 -08:00 |
|
cturek
|
78c2ce5649
|
Updated testbench/wave for fdivsqrt new start signals
|
2022-11-22 22:22:26 +00:00 |
|
cturek
|
9d30a832c3
|
Reoredered tests for arch32m
|
2022-11-09 18:42:00 +00:00 |
|
cturek
|
2cbe2fd70b
|
Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
|
2022-11-06 22:08:18 +00:00 |
|
David Harris
|
53a88fec8f
|
Reorder embench tests to prevent crash
|
2022-11-04 15:21:51 -07:00 |
|
Ross Thompson
|
a59df0c77d
|
Created one off test to replicate the floating point forwarding hazard bug.
|
2022-10-22 16:29:12 -05:00 |
|
Kip Macsai-Goren
|
c18c181fc0
|
fixed endianness mstatush problem, passes make, not regression
|
2022-10-04 17:37:39 +00:00 |
|