13 Commits

Author	SHA1	Message	Date
Matthew	9514eab75e	Implement progbuf and attempt to halt/resume using existing trap logic (very broken)	2024-06-19 23:06:16 -05:00
Matthew	7dd0182407	add progbuff write logic stub	2024-06-16 15:21:02 -05:00
Matthew	60f12a6f60	Fix DPC write and DCSR Cause	2024-06-14 18:27:06 -05:00
Matthew	6ae7ac9a6d	Implement DCSR (Writes are broken)	2024-06-14 00:35:20 -05:00
Matthew	6f1f3b719a	Alls CSRS tested (Read only)	2024-06-12 10:28:42 -05:00
Matthew	c8e5a33ae7	cleanup repo, still WIP	2024-06-11 23:04:44 -05:00
Matthew	abff0bbab4	(WIP) make all CSRs scannable by DM	2024-06-11 22:42:30 -05:00
James Stine	4675614802	another csr debug.vh update	2024-06-09 23:47:04 -05:00
James Stine	d2f55b44f5	update csrs so there is a record of them	2024-06-09 23:33:24 -05:00
Matthew	5ba6e4da0f	DM accesses to DPC address point to PCM	2024-06-09 15:42:21 -05:00
James Stine	130715a58f	mod debug.sh to have FP regs	2024-06-06 15:56:47 -05:00
Matthew	d900f68acd	make requested changes	2024-06-04 12:11:11 -05:00
James Stine	77ec3d58c6	seed debug module for Wally	2024-06-03 16:37:13 -05:00