mirror of
https://github.com/openhwgroup/cvw
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211 lines
6.2 KiB
Systemverilog
Executable File
211 lines
6.2 KiB
Systemverilog
Executable File
///////////////////////////////////////////
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// debug.vh
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//
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// Written: matthew.n.otto@okstate.edu
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// Created: 15 March 2024
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//
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// Purpose: debug port definitions
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// DMI op field constants
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`define OP_NOP 2'b00
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`define OP_READ 2'b01
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`define OP_WRITE 2'b10
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`define OP_SUCCESS 2'b00
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`define OP_FAILED 2'b10
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`define OP_BUSY 2'b11
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// Debug Bus Address Width
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`define ADDR_WIDTH 7
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// Debug Module Debug Bus Register Addresses
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// DM Internal registers
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`define DATA0 `ADDR_WIDTH'h04
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`define DATA1 `ADDR_WIDTH'h05
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`define DATA2 `ADDR_WIDTH'h06
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`define DATA3 `ADDR_WIDTH'h07
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`define DATA4 `ADDR_WIDTH'h08
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`define DATA5 `ADDR_WIDTH'h09
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`define DATA6 `ADDR_WIDTH'h0A
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`define DATA7 `ADDR_WIDTH'h0B
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`define DATA8 `ADDR_WIDTH'h0C
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`define DATA9 `ADDR_WIDTH'h0D
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`define DATA10 `ADDR_WIDTH'h0E
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`define DATA11 `ADDR_WIDTH'h0F
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`define DMCONTROL `ADDR_WIDTH'h10
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`define DMSTATUS `ADDR_WIDTH'h11
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`define HARTINFO `ADDR_WIDTH'h12
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`define ABSTRACTCS `ADDR_WIDTH'h16
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`define COMMAND `ADDR_WIDTH'h17
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`define ABSTRACTAUTO `ADDR_WIDTH'h18
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`define NEXTDM `ADDR_WIDTH'h1d
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//`define dmcs2 `ADDR_WIDTH'h32
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`define SBCS `ADDR_WIDTH'h38
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//// Register field ranges
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// DMCONTROL 0x10
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`define HALTREQ 31
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`define RESUMEREQ 30
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`define HARTRESET 29
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`define ACKHAVERESET 28
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`define ACKUNAVAIL 27
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`define HASEL 26
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`define HARTSELLO 25:16
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`define HARTSELHI 15:6
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`define SETKEEPALIVE 5
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`define CLRKEEPALIVE 4
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`define SETRESETHALTREQ 3
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`define CLRRESETHALTREQ 2
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`define NDMRESET 1
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`define DMACTIVE 0
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// DMSTATUS 0x11
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`define NDMRESETPENDING 24
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`define STICKYUNAVAIL 23
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`define IMPEBREAK 22
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`define ALLHAVERESET 19
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`define ANYHAVERESET 18
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`define ALLRESUMEACK 17
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`define ANYRESUMEACK 16
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`define ALLNONEXISTENT 15
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`define ANYNONEXISTENT 14
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`define ALLUNAVAIL 13
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`define ANYUNAVAIL 12
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`define ALLRUNNING 11
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`define ANYRUNNING 10
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`define ALLHALTED 9
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`define ANYHALTED 8
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`define AUTHENTICATED 7
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`define AUTHBUSY 6
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`define HASRESETHALTREQ 5
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`define CONFSTRPTRVALID 4
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`define VERSION 3:0
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// ABSTRACTCS 0x16
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`define PROGBUFSIZE 28:24
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`define BUSY 12
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`define RELAXEDPRIV 11
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`define CMDERR 10:8
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`define DATACOUNT 3:0
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// COMMAND 0x17
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`define CMDTYPE 31:24
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`define CONTROL 23:0
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//// Abstract Commands
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// cmderr
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`define CMDERR_NONE 3'h0
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`define CMDERR_BUSY 3'h1
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`define CMDERR_NOT_SUPPORTED 3'h2
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`define CMDERR_EXCEPTION 3'h3
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`define CMDERR_HALTRESUME 3'h4
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`define CMDERR_BUS 3'h5
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`define CMDERR_OTHER 3'h7
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// Abstract CmdType Constants (3.7.1)
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`define ACCESS_REGISTER 0
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`define QUICK_ACCESS 1
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`define ACCESS_MEMORY 2
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// ACCESS_REGISTER Control ranges
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`define AARSIZE 22:20
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`define AARPOSTINCREMENT 19
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`define POSTEXEC 18
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`define TRANSFER 17
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`define AARWRITE 16
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`define REGNO 15:0
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// aarsize
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`define AAR32 2
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`define AAR64 3
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`define AAR128 4
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// Register Numbers (regno)
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// (Table 3.3)
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// 0x0000 – 0x0fff | CSRs. The “PC” can be accessed here through dpc.
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// 0x1000 – 0x101f | GPRs
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// 0x1020 – 0x103f | Floating point registers
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// 0xc000 – 0xffff | Reserved for non-standard extensions and internal use.
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// privileged/csr/csrm
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`define MISA 16'h0301 // XLEN P.ZICSR_SUPPORTED (Read Only)
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// wallypipelinedcore
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`define TRAPM 16'hC000 // 1'b P.ZICSR_SUPPORTED (Read Only)
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// src/ifu
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`define PCM 16'hC001 // XLEN P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED
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`define INSTRM 16'hC002 // 32'b P.ZICSR_SUPPORTED | P.A_SUPPORTED
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// ieu/controller
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`define MEMRWM 16'hC003 // 2'b
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`define INSTRVALIDM 16'hC004 // 1'b
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// ieu/datapath
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`define WRITEDATAM 16'hC005 // XLEN
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// lsu
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`define IEUADRM 16'hC006 // XLEN
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`define READDATAM 16'hC007 // LLEN (Read Only)
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// src/ieu/datapath
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`define X0 16'h1000
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`define X1 16'h1001
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`define X2 16'h1002
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`define X3 16'h1003
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`define X4 16'h1004
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`define X5 16'h1005
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`define X6 16'h1006
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`define X7 16'h1007
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`define X8 16'h1008
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`define X9 16'h1009
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`define X10 16'h100A
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`define X11 16'h100B
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`define X12 16'h100C
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`define X13 16'h100D
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`define X14 16'h100E
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`define X15 16'h100F
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`define X16 16'h1010 // E_SUPPORTED
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`define X17 16'h1011 // E_SUPPORTED
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`define X18 16'h1012 // E_SUPPORTED
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`define X19 16'h1013 // E_SUPPORTED
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`define X20 16'h1014 // E_SUPPORTED
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`define X21 16'h1015 // E_SUPPORTED
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`define X22 16'h1016 // E_SUPPORTED
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`define X23 16'h1017 // E_SUPPORTED
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`define X24 16'h1018 // E_SUPPORTED
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`define X25 16'h1019 // E_SUPPORTED
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`define X26 16'h101A // E_SUPPORTED
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`define X27 16'h101B // E_SUPPORTED
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`define X28 16'h101C // E_SUPPORTED
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`define X29 16'h101D // E_SUPPORTED
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`define X30 16'h101E // E_SUPPORTED
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`define X31 16'h101F // E_SUPPORTED
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// ACCESS_MEMORY Control ranges (Not implemented)
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//`define AAMVIRTUAL 23
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//`define AAMSIZE 22:20
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//`define AAMPOSTINCREMENT 19
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//`define AAMWRITE 16
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//`define TARGET_SPECIFIC 15:14
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// aamsize
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//`define AAM8 0
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//`define AAM16 1
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//`define AAM32 2
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//`define AAM64 3
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//`define AAM128 4
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