Ross Thompson
93fb8db9bb
Moved amoalu to lsu.
2023-01-17 22:45:46 -06:00
Ross Thompson
cd5e62119a
Added commenets and formating to abhcachefsm and abhcacheinterface.
2023-01-17 22:22:23 -06:00
Ross Thompson
c3096eea2a
Cleaned up ahbcacheinterface.
2023-01-17 22:13:56 -06:00
Ross Thompson
4720b28272
Formatting progress.
2023-01-17 22:10:31 -06:00
Ross Thompson
d21eef40d7
Added comments to dtim and ahbcacheinterface.
2023-01-17 21:56:55 -06:00
David Harris
94d01d292e
ebu cleanup
2023-01-14 19:29:45 -08:00
David Harris
17fd2d2a3b
ebu cleanup
2023-01-14 19:19:34 -08:00
David Harris
b4dd7b21e6
generic cleanup
2023-01-14 19:02:38 -08:00
David Harris
7d93659f6b
changed name to CORE-V-WALLY
2023-01-11 15:15:08 -08:00
David Harris
b911056e66
Changed Wally to CORE-V Wally
2023-01-11 14:03:44 -08:00
David Harris
e92cffbb5e
Changed MIT license to Solderpad License
2023-01-10 11:35:20 -08:00
David Harris
5fbba604f1
Remove unused CACHE_ENABLED parameter
2023-01-07 09:57:24 -08:00
David Harris
cdcee61aac
vclean working; started removing unused signals
2023-01-07 05:34:58 -08:00
Ross Thompson
ce7e1073fa
Success we've replaced TrapM with FlushD in the IFU.
2022-12-22 21:36:49 -06:00
Ross Thompson
942acb354e
Closing in on icache flushed by FlushD rather than TrapM.
2022-12-22 20:19:09 -06:00
Ross Thompson
47d61984ad
First pass at resolving ifu flush on trap rather than FlushD.
2022-12-22 15:53:06 -06:00
Ross Thompson
ab3c5a0ca7
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
Ross Thompson
6d573b32d2
Changed CPUBusy to Stall in ebu modules.
2022-12-11 15:51:35 -06:00
Ross Thompson
54544ae251
Moved all remaining bus logic from the LSU into ahbcacheinterface.
2022-11-11 14:30:32 -06:00
Ross Thompson
8658a25218
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
028e2b0f91
Renamed CACHE_EVICT to CACHE_WRITEBACK.
2022-11-09 17:43:06 -06:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
Ross Thompson
65c2fe294a
Merged cacheable with seluncachedadr.
2022-10-17 13:29:21 -05:00
Ross Thompson
bf6f0e7219
Fixed bug in EBU.
2022-10-05 14:51:12 -05:00
Ross Thompson
ea70e1c598
Optimized the ebu's beat counting.
2022-10-05 10:58:23 -05:00
Ross Thompson
e27fcb1577
Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage.
2022-09-29 18:37:34 -05:00
Ross Thompson
2c0132aa9c
Renamed signals in EBU.
2022-09-29 18:29:38 -05:00
Ross Thompson
58d597b614
Simplification to EBU.
2022-09-29 18:06:34 -05:00
Ross Thompson
d81af3bca8
Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.
2022-09-29 11:54:03 -05:00
Ross Thompson
32449dfe97
Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
2022-09-28 17:39:51 -05:00
Ross Thompson
4db017dac3
Possible fix for ifu/lsu arbiration issue.
2022-09-27 17:24:35 -05:00
Ross Thompson
4062fe56c0
Possible fix to the bus cache interaction.
2022-09-27 11:34:33 -05:00
Ross Thompson
996c4ca8f2
renamed ahbmulticontroller to ebu.
2022-09-26 14:37:18 -05:00
Ross Thompson
0fcc314d06
Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
2022-09-26 12:48:26 -05:00
Ross Thompson
38edbde966
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
...
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
2022-09-23 11:46:53 -05:00
Ross Thompson
bcca9a62c5
Fixed up IFU ahb interface names and widths.
2022-09-19 10:54:22 -05:00
Ross Thompson
cb34b7c98f
Found the ahb burst bug.
...
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
2022-09-17 20:30:01 -05:00
Ross Thompson
cea012a640
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
2c86badeb2
pipelining of fetch into evict AHB requests.
2022-09-13 17:51:55 -05:00
Ross Thompson
0904951a8c
Oups the ahbinterface.sv was accidentally named abhinterface.sv.
2022-09-08 13:21:37 -05:00
Ross Thompson
bc15f6c5e4
Added logic to make burst optional.
2022-09-06 09:21:21 -05:00
Ross Thompson
20643ffc4a
Names changes.
2022-09-05 20:49:35 -05:00
Ross Thompson
2554f96662
Cleaned up hacks to ram.
2022-09-04 14:52:40 -05:00
Ross Thompson
221367efb9
Disabled AHB burst mode, which discovered a bug.
...
Multimanger bug in how back to back requests were arbitrated.
2022-09-03 22:31:41 -05:00
Ross Thompson
00cffb0aa5
Renamed state in buscachefsm to match AHB phases.
2022-09-02 17:17:40 -05:00
Ross Thompson
6f2acf678c
Renamed states in busfsm to match AHB phases and book names.
2022-09-02 17:12:36 -05:00
Ross Thompson
6f366c643d
Possible fix for AHB trailing ~HREADY bug.
2022-09-02 16:58:35 -05:00
Ross Thompson
eae56a890c
marked possible improvement to ahb bus fsms.
2022-08-31 23:57:08 -05:00
Ross Thompson
7598fbcb3b
Reduced busfsm to 3 states!
2022-08-31 16:11:59 -05:00
Ross Thompson
6f3dad8207
Simplified.
2022-08-31 15:40:56 -05:00
