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2,281 Commits 5 Branches 2 Tags 53 MiB
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Commit Graph

34 Commits

Author SHA1 Message Date
David Harris
f9ab193ca8 Added partially working MMU tests 2021-12-29 03:14:16 +00:00
David Harris
6e20d011d5 Fixed imperas C tests 2021-12-26 04:45:06 +00:00
Ross Thompson
596cc4fde4 Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card. 
mv qemu patches to tests directory.
 2021-12-19 20:11:32 -06:00
Ross Thompson
a871118116 Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
Ross Thompson
5642918ead Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
bbracker
23194c0308 fix parseState.py to correctly take in PMPCFG 2021-11-24 16:52:51 -08:00
bbracker
cf27cc7fcd increase niceness of automatic checkpoint generation 2021-11-20 12:48:23 -08:00
David Harris
690410721d Cleaning up CoreMark benchmark 2021-11-18 20:12:52 -08:00
David Harris
8e8b84f532 vert "Simplifying riscv-coremark" 
This reverts commit ce8232e396.
 2021-11-18 18:40:13 -08:00
David Harris
ce8232e396 Simplifying riscv-coremark 2021-11-18 17:15:40 -08:00
David Harris
402b473dbb CoreMark testing 2021-11-18 16:14:25 -08:00
David Harris
c610be25a7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-16 12:30:55 -08:00
bbracker
2203590f9f get current privilege level from GDB for checkpoints 2021-11-15 14:49:00 -08:00
David Harris
570f24a9e4 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
bbracker
e4da379340 genCheckpoint path bugfix 2021-11-06 15:25:10 -07:00
bbracker
9f2a583590 automated checkpoint generator 2021-11-06 14:37:49 -07:00
bbracker
97403af403 update tvLinker to new shared dir 2021-11-06 14:15:16 -07:00
bbracker
8c926dcfd2 make genCheckpoint accept instr count as argument 2021-11-06 14:14:15 -07:00
bbracker
bc6332a780 fix merge conflict 2021-11-05 23:42:15 -07:00
bbracker
17e776f853 checkpoints now use binary ram files 2021-11-05 22:37:05 -07:00
bbracker
9fe8820ed0 genCheckpoint syntax fix 2021-11-01 15:31:38 -07:00
bbracker
526aff54a8 linux testgen refactor 2021-11-01 14:09:49 -07:00
David Harris
0cc71f1dec added some missing files 2021-11-01 13:36:07 -07:00
David Harris
d449795b3e simplified header and footer 2021-11-01 13:24:18 -07:00
David Harris
d7f0abca5a Add3d wally32i test 2021-11-01 13:17:49 -07:00
David Harris
dda035891a PIPELINE test running 2021-11-01 12:44:35 -07:00
David Harris
60573b92b2 Adding custom Wally test infrastructure 2021-11-01 08:48:46 -07:00
David Harris
247f247ad3 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00
David Harris
14b9b8126e rearranging testgen 2021-10-29 22:28:37 -07:00
David Harris
67adc1d7d5 removed referenc outputs 2021-10-26 08:51:49 -07:00
Ross Thompson
81054d9168 Fixed issue with dtim (fpga) external abhlite select not triggering. 
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
 2021-10-25 14:51:54 -05:00
David Harris
0dabb6ebd4 lint cleaning and moved files into subdirectories 2021-10-23 08:53:32 -07:00
Ross Thompson
de4ea16d32 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
David Harris
23b3d7dbc1 Move tests into subdirectory and moved wavedrom out of project 2021-10-20 09:03:21 -07:00