Ross Thompson
b4bdf446cc
Implement FENCE.I as NOP when ZIFENCEI is not supported.
2022-12-20 17:34:11 -06:00
Ross Thompson
d9a1870a31
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 17:11:35 -06:00
Ross Thompson
ef4ecbe62b
Changed long names of vectored pcm signals.
2022-12-20 17:01:20 -06:00
David Harris
f03d4e6b5a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-20 14:43:33 -08:00
David Harris
9133b3a7a4
FPU remove unused signals
2022-12-20 14:43:30 -08:00
Ross Thompson
be1bbf486e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 16:36:44 -06:00
Ross Thompson
637df763ca
Renumbered bits for PCPlusUpper.
2022-12-20 16:33:49 -06:00
David Harris
4c4b8db498
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-20 11:23:53 -08:00
David Harris
8f0ef29349
Memory cleanup
2022-12-20 11:22:26 -08:00
Ross Thompson
ca6076445b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 12:58:59 -06:00
Ross Thompson
d35fc5e2a6
Reorganized IFU PCNextF logic.
2022-12-20 12:58:54 -06:00
David Harris
00ff823d84
Restored rv32d arch test after new push
2022-12-20 10:56:33 -08:00
David Harris
c26c3b76ea
Renamed renamed sram to ram
2022-12-20 08:36:45 -08:00
David Harris
1ec62606f9
sram1p1rw cleanup
2022-12-20 02:57:51 -08:00
David Harris
0883736c88
Remoed unused bram modules
2022-12-20 02:40:45 -08:00
David Harris
9ad5552e89
Renamed SRAM2P1R1W to lower case
2022-12-20 02:09:55 -08:00
David Harris
b575f6242e
Renamed SRAM2P1R1W to lower case
2022-12-20 02:09:36 -08:00
David Harris
0c10ec942a
Replaced || and && with single ops
2022-12-20 01:33:35 -08:00
Ross Thompson
67e0b021ae
several options for pcnextf on fence.i
2022-12-19 23:33:12 -06:00
Ross Thompson
d18ef45c18
More bp/ifu pcmux cleanup.
2022-12-19 23:16:58 -06:00
Ross Thompson
761cf54dcc
Moved more muxes inside bp.
2022-12-19 22:51:55 -06:00
Ross Thompson
0097c166d6
Begin cleanup of ifu. partial move of pc muxes inside bp.
2022-12-19 22:46:11 -06:00
David Harris
954051da13
Removed CSR support from rv32i
2022-12-19 16:15:12 -08:00
David Harris
2393915bf2
Simplified InstrRawD register
2022-12-19 15:18:42 -08:00
David Harris
aac4b55b59
Explained hazard causes
2022-12-19 09:41:41 -08:00
David Harris
16b8fbbd2d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-19 09:09:57 -08:00
David Harris
b5958b1e11
Properly decode fcvtint to prevent unnecessary stalls
2022-12-19 09:09:48 -08:00
Ross Thompson
ddde82f928
Renamed FStallD to FPUStallD.
2022-12-19 09:28:45 -06:00
Alessandro Maiuolo
13c9f2e4a5
Added NumZeroE, AZeroM, and BZeroM
2022-12-18 20:02:40 -08:00
Alessandro Maiuolo
3bcb42adb6
fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)
2022-12-18 19:04:36 -08:00
Ross Thompson
6f6cda5f0e
Added files to gitignore.
2022-12-18 18:53:37 -06:00
Ross Thompson
c3b77926d5
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
2022-12-18 18:30:35 -06:00
Ross Thompson
e8c1d14abb
Have a basic cache test to fill all ways and sets.
2022-12-18 17:20:30 -06:00
Ross Thompson
7a352edf13
Attempted to make a cache test.
2022-12-18 17:15:08 -06:00
Ross Thompson
9d1cb9337e
Updated tests for fpga and BP.
2022-12-18 16:24:26 -06:00
Ross Thompson
13beda7d0c
Updated vcu118 piniout.
2022-12-18 14:00:10 -06:00
Ross Thompson
5acdf541b9
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
9849983348
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
c985988867
Fixed a bug with the new cache flush changes.
2022-12-16 19:28:32 -06:00
Ross Thompson
9b9e954cc5
Cleanup comments.
2022-12-16 17:08:35 -06:00
Ross Thompson
5f556817c7
Further cleanfsm cleanup.
2022-12-16 16:37:45 -06:00
Ross Thompson
493b1a4280
More cachefsm cache flush cleanup.
2022-12-16 16:32:21 -06:00
Ross Thompson
3132246a46
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
698ca7d482
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-16 15:37:03 -06:00
Ross Thompson
91e64a0d67
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
ab3c5a0ca7
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
cturek
0ceecd9961
Added integer support for initC
2022-12-16 19:02:11 +00:00
Ross Thompson
9c67972b21
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-16 12:52:22 -06:00
Ross Thompson
f04ca5cb6a
Fixed regression-wally to correct remove and mkdir wkdir.
2022-12-16 12:51:21 -06:00
cturek
9340a5eb49
Added mux for integer special case, renamed signals to match pipelined stage
2022-12-16 18:43:49 +00:00
