27 Commits

Author	SHA1	Message	Date
David Harris	b911056e66	Changed Wally to CORE-V Wally	2023-01-11 14:03:44 -08:00
David Harris	e6f110b953	Replaced MDUE with IntDivE in FDIVSQRT	2023-01-11 11:06:37 -08:00
David Harris	e92cffbb5e	Changed MIT license to Solderpad License	2023-01-10 11:35:20 -08:00
David Harris	0a011f4548	Remove unused signals	2023-01-07 05:46:22 -08:00
David Harris	6d22c73676	Branch logic simplification and remove unused signals	2023-01-07 05:42:34 -08:00
David Harris	921b5582da	ALU cleanup	2022-12-24 07:18:35 -08:00
David Harris	07dc11a508	IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI	2022-12-20 15:38:30 -08:00
Ross Thompson	b4bdf446cc	Implement FENCE.I as NOP when ZIFENCEI is not supported.	2022-12-20 17:34:11 -06:00
Ross Thompson	c253b882be	Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.	2022-12-15 09:53:35 -06:00
David Harris	643a2e7cf9	Use FPU divider for integer division when F is supported	2022-12-14 17:03:13 -08:00
David Harris	46680b80a7	Eliminated store after store stall when no cache; simplified divshiftcalc logic.	2022-09-21 13:02:34 -07:00
Ross Thompson	51adf6cba9	Modified the lsu/ifu memory configurations.	2022-08-24 12:35:15 -05:00
Madeleine Masser-Frye	3c08861479	switched comparator to dc flip version	2022-06-21 20:30:33 +00:00
David Harris	9065b684f8	Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit	2022-06-02 09:37:59 -07:00
David Harris	7cf5d481c0	Cleaned up comments in controller	2022-06-02 15:48:33 +00:00
David Harris	61199ccd13	More signal cleanup	2022-05-12 15:39:44 +00:00
David Harris	9c4de0e9c1	FPU generates illegal instruction if MSTATUS.FS = 00	2022-05-03 11:56:31 +00:00
David Harris	48705457d5	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
David Harris	b537df2651	Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0	2022-02-12 05:50:34 +00:00
David Harris	15fb7fee60	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
David Harris	0feb624bab	Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration	2022-02-06 01:22:40 +00:00
David Harris	bdf1a8ba73	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
David Harris	de7b9c127e	Added E extension, and downloaded riscv-dv and embench-iot to addins	2022-01-17 14:42:59 +00:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	2df92af488	Capitalized LSU and IFU, changed MulDiv to MDU	2022-01-07 04:30:00 +00:00
David Harris	d66f7c841b	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00