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Author SHA1 Message Date
slmnemo
a5aa75e5de Merge branch 'main' into cacheburstmode 2022-06-08 02:21:33 +00:00
slmnemo
1d22fc707a Added lock signal to ensure AHB speaks with the right bus 2022-06-08 02:19:21 +00:00
David Harris
b53aef33f5 Modified RAM for single-cycle latency 2022-06-08 02:06:00 +00:00
David Harris
cc06fa1c55 Cleaned bram interface 2022-06-08 01:39:44 +00:00
David Harris
f81719337e Added ahbapbbridge and cleaning RAM 2022-06-08 01:31:34 +00:00
DTowersM
1d41e98504 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-07 23:58:58 +00:00
DTowersM
3d654fd481 modified testbench.sv- now works with coremark 2022-06-07 23:58:50 +00:00
DTowersM
930c806753 cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000 2022-06-07 23:27:54 +00:00
slmnemo
85801e75db Fixed off-by-one error in busdp capture 2022-06-07 19:36:39 +00:00
Madeleine Masser-Frye
fcf1cb794e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-07 18:31:54 +00:00
Madeleine Masser-Frye
8849b47b52 fixed importing of area-optimized synths, overlayed them on PPA plots, accounted for mux outliers, fixed flop adjustments 2022-06-07 18:31:49 +00:00
slmnemo
90c5e5d319 Reworked bus to handle burst interfacing 2022-06-07 11:22:53 +00:00
DTowersM
4cadf139a6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-07 06:03:19 +00:00
DTowersM
fbfae61ba8 added support for 64 bit rv tests 2022-06-07 06:02:23 +00:00
DTowersM
0e7630dc03 simplified makefile. Now can call modelsim to run embench runs. Additionally added spike builds to be able to run the embench tests on spike. typing make now builds all necessary files and starts the simulator on the embench 2022-06-06 22:39:22 +00:00
Katherine Parry
b8cff98e48 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-06 16:06:54 +00:00
Katherine Parry
eb93bd46d7 fma synth warnings and errors removed 2022-06-06 16:06:04 +00:00
Ross Thompson
83bca570ae Modified debugger for updated rtl. 2022-06-04 14:39:55 -05:00
slmnemo
3a276f4c39 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-03 18:56:29 -07:00
slmnemo
8c3d7b404b Fixed recurrent issue with testbench where it would never stop 2022-06-03 18:56:24 -07:00
cturek
0e308cfccc Added integer division in srt, parametrized everything to work with integers and floating points, parametrized testbench. 2022-06-04 00:14:10 +00:00
Madeleine Masser-Frye
fc1860615f added area, leakage, energy, adjustment by adder width (N/32) 2022-06-03 23:51:34 +00:00
Madeleine Masser-Frye
92d9687ded added combined process regression line 2022-06-03 22:53:03 +00:00
Madeleine Masser-Frye
b1571f7ee9 removing plots and archived runs from repo 2022-06-03 22:15:51 +00:00
DTowersM
23d524b439 testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh 2022-06-03 22:07:14 +00:00
Madeleine Masser-Frye
0ef0c5498a stop tracking runArchive and ppa plots 2022-06-03 22:03:26 +00:00
Madeleine Masser-Frye
f6f561e8fd plots and synth runs 2022-06-03 21:23:04 +00:00
Madeleine Masser-Frye
5a9f1a3970 update 2022-06-03 21:17:50 +00:00
Madeleine Masser-Frye
2383ca4f53 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-03 21:08:49 +00:00
Madeleine Masser-Frye
6c6a12cfd5 added muxes and inv, fixed priority encoder 2022-06-03 21:03:13 +00:00
Katherine Parry
b785b6a9bc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-03 15:34:27 +00:00
Katherine Parry
5ae63f913a fixed compilation errors 2022-06-03 15:34:17 +00:00
slmnemo
0011a1b269 Changed NO_SPOOFING from 0 to 1 in buildroot-no-trace to better facilitate wally booting linux without following QEMU's trace 2022-06-03 04:55:14 -07:00
Katherine Parry
019994c802 removed some debuging code accedentally pushed 2022-06-02 22:45:19 +00:00
Katherine Parry
dfec6bda8a added rv64fpquad 2022-06-02 22:10:00 +00:00
Katherine Parry
39101fcbb3 added config rv64fpquad 2022-06-02 22:09:11 +00:00
David Harris
12399ba924 renamed sim-fp to sim-testfloat 2022-06-02 15:05:29 -07:00
Katherine Parry
b6b3f04af2 added create all vectores file 2022-06-02 21:56:47 +00:00
Katherine Parry
c5bde75e30 added createallvectors 2022-06-02 21:56:05 +00:00
David Harris
66330ca6e9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-02 20:50:56 +00:00
Katherine Parry
9cc8625ce0 removed fp vectors 2022-06-02 20:50:32 +00:00
David Harris
1175aa1abd Reverted fp testcase ignore 2022-06-02 20:50:23 +00:00
David Harris
7f174310b9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-02 20:48:34 +00:00
David Harris
08714ca53f mulAdd tests in gitignore 2022-06-02 20:48:14 +00:00
Katherine Parry
43dbbde51f added testvectors fp 2022-06-02 20:48:10 +00:00
slmnemo
b35824eadd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-02 12:54:08 -07:00
Katherine Parry
ccda4c771e fpu paramaterized - except fdivsqrt 2022-06-02 19:50:28 +00:00
slmnemo
568b83a647 Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do" 
This reverts commit 7d2bfb6db8.
 2022-06-02 12:45:21 -07:00
slmnemo
40abe59d33 Revert "Fixed buildroot by adding a second ." 
This reverts commit 0982417054.
 2022-06-02 12:43:59 -07:00
slmnemo
581c950193 Revert "Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py" 
This reverts commit 05d14bdb3c.
 2022-06-02 12:41:01 -07:00