30 Commits

Author	SHA1	Message	Date
David Harris	9a17556de4	Start to parameterize number of PMP Entries	2021-06-08 15:29:22 -04:00
Kip Macsai-Goren	6ed96761b6	Merge small mmu changes into main	2021-06-08 14:00:26 -04:00
Kip Macsai-Goren	be99c18002	making mmu branch line up with main	2021-06-08 13:59:03 -04:00
Kip Macsai-Goren	41ceb20296	some cleanup of signals, not done yet	2021-06-08 13:39:32 -04:00
bbracker	17960a6484	Ah big ole merge! Passes sim-wally-batch and linting, so should be fine	2021-06-08 12:41:25 -04:00
bbracker	5026a42fac	* GPIO comprehensive testing ... * MEPC more aware if M stage has actually committed * UART interrupt testing progress * UART added read IIR side effect of lowering THRE intr	2021-06-08 12:32:46 -04:00
Kip Macsai-Goren	d69501c4fa	Cleaned up some unused signals	2021-06-04 21:04:19 -04:00
Kip Macsai-Goren	7e41b17e65	restructured so that pma/pmp are a part of mmu	2021-06-04 17:05:07 -04:00
bbracker	28abd28b1f	fixed InstrValid signals and implemented less costly MEPC loading	2021-06-02 10:03:19 -04:00
bbracker	8d77012995	progress on bus and lrsc	2021-04-26 07:43:16 -04:00
Ross Thompson	d7fea1ba3c	almost working icache.	2021-04-23 16:47:23 -05:00
Ross Thompson	c9bdaceddb	Fixed icache for 32 bit. ... Merge branch 'cache' into main	2021-04-22 16:45:29 -05:00
Ross Thompson	04eb302925	Yes. The hack to not repeat the d memory operation fixed this issue.	2021-04-22 15:22:56 -05:00
Thomas Fleming	70c801331a	Implement virtual memory protection	2021-04-21 19:58:36 -04:00
Jarred Allen	3868a82932	dcache lints	2021-04-15 21:13:56 -04:00
Thomas Fleming	e807f5d771	Implement support for superpages	2021-04-08 02:44:59 -04:00
Thomas Fleming	4b2765f8e2	Complete basic page table walker	2021-03-30 22:19:27 -04:00
Thomas Fleming	062c4d40da	Connect tlb, pagetablewalker, and memory	2021-03-18 14:35:46 -04:00
Thomas Fleming	e57b6cf18c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ebu/ahblite.sv	2021-03-11 00:15:58 -05:00
David Harris	fe4d288589	Initial untested implementation of AMO instructions	2021-03-11 00:11:31 -05:00
David Harris	bea8ac6d59	WALLY-LRSC atomic test passing	2021-03-09 09:28:25 -05:00
Thomas Fleming	e48dc38869	Export SATP_REGW from csrs to MMU modules	2021-03-05 01:22:53 -05:00
Thomas Fleming	8c410b6fbe	Install dtlb in dmem	2021-03-04 03:30:06 -05:00
David Harris	6f4e8b723e	Initial (untested) implementation of lr and sc	2021-03-01 00:09:45 -05:00
David Harris	225102047a	Clean up bus interface code	2021-02-26 01:03:47 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	429f48e766	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	bb83fda1d8	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	92bf1674b4	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	1a3963bed0	Renamed DCU to DMEM	2021-02-01 18:52:22 -05:00