David Harris
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f4957fdac1
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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David Harris
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b42faa794a
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changed ideal memory to MEM_DTIM and MEM_ITIM
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2021-12-14 13:05:32 -08:00 |
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Ross Thompson
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74ffb48c0a
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Mostly integrated FPGA flow into main branch. Not all tests passing yet.
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2021-12-02 18:00:32 -06:00 |
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Ross Thompson
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5fdac9fa3b
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Merge branch 'main' into fpga
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2021-10-11 18:17:58 -05:00 |
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Shreya Sanghai
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51185478df
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made redunantmul generate DW02_multp for synopsys sythnesis
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2021-10-11 11:54:39 -07:00 |
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David Harris
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a077735ecc
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Major reorganization of regression and simulation and testbenches
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2021-10-10 15:07:51 -07:00 |
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David Harris
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30ec68d567
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Parameterized number of bits per cycle for integer division
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2021-10-03 01:10:15 -04:00 |
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Ross Thompson
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99070127d8
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Added debugging directives to system verilog.
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2021-09-27 13:57:46 -05:00 |
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Ross Thompson
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4256ef82b1
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SDC to ABHLite interface partially done.
Added SDC to adrdec and uncore.
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2021-09-24 10:45:09 -05:00 |
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David Harris
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72c1cc33f5
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Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
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2021-09-15 13:14:00 -04:00 |
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Ross Thompson
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8141a515bb
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Changed configs to support 4 ways set associative caches.
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2021-09-08 12:52:49 -05:00 |
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Ross Thompson
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d430659983
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fixed the read timer issue but we still have problems with interrupts and i/o devices.
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2021-08-06 10:16:06 -05:00 |
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David Harris
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c117356432
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Parameterized I$/D$ configurations and added sanity check assertions in testbench
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2021-07-20 08:57:13 -04:00 |
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David Harris
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b2f7952b3d
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Added cache configuration to config files
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2021-07-19 18:19:46 -04:00 |
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David Harris
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c29a2ff8df
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Started atomics
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2021-07-17 21:11:41 -04:00 |
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David Harris
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f69393f197
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Reduced size of physical memory by 16 for performance
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2021-07-16 20:10:12 -04:00 |
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Ross Thompson
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abce241f68
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Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
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2021-07-16 14:21:09 -05:00 |
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David Harris
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6b9cfe90d8
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Added ASID & Global PTE handling to TLB CAM
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2021-07-04 17:52:00 -04:00 |
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David Harris
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c897bef8cd
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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Kip Macsai-Goren
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1485d29dde
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Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
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2021-06-24 20:01:11 -04:00 |
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bbracker
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83a1f29c37
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
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2021-06-20 22:38:25 -04:00 |
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David Harris
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72d8d34e3c
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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09c5e27853
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Started simplifying PMA checker
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2021-06-17 16:28:06 -04:00 |
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David Harris
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e231fc6b00
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More verilator fixes, but bpred is broken
|
2021-06-09 21:03:03 -04:00 |
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David Harris
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4bd7058456
|
More PMP entries
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2021-06-08 15:33:06 -04:00 |
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David Harris
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9a17556de4
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Start to parameterize number of PMP Entries
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2021-06-08 15:29:22 -04:00 |
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Kip Macsai-Goren
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fcb9b1f0e1
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working version with new mmu comments, old boottim values
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2021-06-08 15:20:25 -04:00 |
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David Harris
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cfe5c27946
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Resized BOOT TIM to 1 KB
|
2021-06-08 14:04:32 -04:00 |
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David Harris
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b37bcc8e38
|
Continued merge
|
2021-06-07 12:49:47 -04:00 |
|
David Harris
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1e67db2f0c
|
Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
|
David Harris
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95cc70295b
|
Merge difficulties
|
2021-06-07 09:50:23 -04:00 |
|
David Harris
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8bbabb683d
|
Refactored configuration files and renamed testbench-busybear to testbench-linux
|
2021-06-07 09:46:52 -04:00 |
|
Kip Macsai-Goren
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b99b5f8e0e
|
moved privilege dfinitions into wally-constants, upgraded relevant includes
|
2021-06-04 17:55:07 -04:00 |
|
David Harris
|
b836679ae1
|
Started MMU
|
2021-06-04 11:59:14 -04:00 |
|
Shriya Nadgauda
|
0be6b81df9
|
finishing merge conflict changes
|
2021-05-03 22:15:05 -04:00 |
|
Shriya Nadgauda
|
52e0b703b7
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merge conflict fixes
|
2021-05-03 22:12:30 -04:00 |
|
Shriya Nadgauda
|
0282aebec7
|
updated pipeline tests
|
2021-05-03 22:07:36 -04:00 |
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bbracker
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0d62440f60
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-30 06:26:35 -04:00 |
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bbracker
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9c08ce5359
|
rv32 plic test and lint fixes
|
2021-04-30 06:26:31 -04:00 |
|
Ross Thompson
|
893e03d55b
|
Fixed memory size in configs for rv32ic and rv64ic.
Removed warning on call to $fscanf.
|
2021-04-29 17:36:46 -05:00 |
|
Ross Thompson
|
14a69c1d06
|
Added the ability to exclude branch predictor.
|
2021-04-26 14:27:42 -05:00 |
|
bbracker
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c796547156
|
greatly improved PLIC register interface
|
2021-04-22 11:22:01 -04:00 |
|
Noah Boorstin
|
5902637632
|
buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
|
2021-04-17 14:44:32 -04:00 |
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bbracker
|
11cf251378
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-04-15 21:09:27 -04:00 |
|
bbracker
|
195cead01c
|
working GPIO interrupt demo
|
2021-04-15 21:09:15 -04:00 |
|
Domenico Ottolia
|
a149f2f3d8
|
Add support for vectored interrupts
|
2021-04-15 19:13:42 -04:00 |
|
Shreya Sanghai
|
75caa65df1
|
Cherry Pick merge of Shreya's localhistory predictor changes into main.
fixed minor bugs in localHistory
|
2021-04-15 09:04:36 -05:00 |
|
bbracker
|
ce7b2314ef
|
Yee hoo first draft of PLIC plus self-checking tests
|
2021-04-04 06:40:53 -04:00 |
|
Thomas Fleming
|
4b2765f8e2
|
Complete basic page table walker
|
2021-03-30 22:19:27 -04:00 |
|
bbracker
|
eea7e2e47e
|
first pass at PLIC interface
|
2021-03-22 10:14:21 -04:00 |
|