DTowersM
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4e5d7ec3d6
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changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
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2022-06-10 00:37:53 +00:00 |
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David Harris
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8066ba45e8
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Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
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2022-05-08 06:46:35 +00:00 |
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Kip Macsai-Goren
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3d1e1202f3
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set WFI timeout to after 16 bits of counting for all configs
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2022-04-28 18:14:08 +00:00 |
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Shreya Sanghai
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c3164f0ce1
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added bpred size to wally config
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2022-04-18 04:21:03 +00:00 |
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David Harris
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2436534687
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First implementation of WFI timeout wait
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2022-04-17 17:20:35 +00:00 |
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Katherine Parry
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20885f4dea
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generating all testfloat vectors
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2022-04-04 17:17:12 +00:00 |
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Ross Thompson
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e802deb4d6
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Can now support the following memory and bus configurations.
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
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2022-03-11 15:18:56 -06:00 |
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bbracker
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6caa97bb26
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change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
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2022-02-22 03:46:08 +00:00 |
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Ross Thompson
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6cd9d84e7f
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New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
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2022-02-17 17:19:41 -06:00 |
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Ross Thompson
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308cc34d6f
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Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
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2022-02-04 23:49:07 -06:00 |
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David Harris
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9e0055cbb9
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More config file cleanup; 32ic tests broken
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2022-02-03 01:08:34 +00:00 |
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David Harris
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bdf1a8ba73
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changed DMEM and IMEM configurations to support BUS/TIM/CACHE
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2022-02-03 00:41:09 +00:00 |
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David Harris
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172a02551b
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Removed Busybear and Buildroot Configuration
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2022-02-02 20:32:22 +00:00 |
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David Harris
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761dae72fe
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Config file & wally-riscv-arch-test cleanup
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2022-02-02 16:35:52 +00:00 |
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David Harris
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c6adb7b6b1
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Updated configs to fix GPIO address to match FU540
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2022-01-26 18:16:34 +00:00 |
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Ross Thompson
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5726b5b640
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Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
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2022-01-13 22:21:43 -06:00 |
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Ross Thompson
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888a60d8d6
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Switched block for line in caches.
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2022-01-04 22:08:18 -06:00 |
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David Harris
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115287adc8
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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