David Harris
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3d13683c07
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Continued framework for B instructions
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2023-01-20 14:27:13 -08:00 |
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Ross Thompson
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340e1797ea
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More cleanup and formatting.
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2023-01-20 12:09:21 -06:00 |
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Ross Thompson
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5b5a615e4a
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Integrated the missing zifence tests into the regression test.
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2023-01-20 10:34:49 -06:00 |
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Ross Thompson
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aa942feedc
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2023-01-17 15:44:44 -06:00 |
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David Harris
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c73bea83cd
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Clean up warnings from Questa
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2023-01-17 13:43:39 -08:00 |
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Ross Thompson
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caff6e788c
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Somehow the imperas files spilled into the main branch.
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2023-01-17 15:39:34 -06:00 |
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David Harris
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efe7e88258
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csr cleanup
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2023-01-13 22:12:06 -08:00 |
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David Harris
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9526479782
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csr cleanup
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2023-01-13 21:25:55 -08:00 |
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Ross Thompson
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76a9e7d963
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Merge branch 'rastemp'
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2023-01-13 18:09:50 -06:00 |
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Ross Thompson
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cf608ee45f
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Possible optimization of gshare.
I don't believe the Writeback stage ghr is needed.
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2023-01-13 12:39:29 -06:00 |
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Ross Thompson
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395b7a5b32
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Nearly complete RVVI tracer.
Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
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2023-01-12 18:43:39 -06:00 |
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Ross Thompson
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ef4c684336
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Added supervisor mode registers to tracer.
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2023-01-12 17:04:41 -06:00 |
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Ross Thompson
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9917be817c
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Added M CSRs to the CSRArray.
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2023-01-12 16:51:51 -06:00 |
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Ross Thompson
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a68773eba1
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added machine csr to logger.
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2023-01-12 16:35:19 -06:00 |
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Ross Thompson
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2e622c9860
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Added support to print the gprs.
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2023-01-12 16:09:30 -06:00 |
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Ross Thompson
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4733b787f8
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rvvi trace is coming alone nicely.
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2023-01-12 14:46:31 -06:00 |
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Ross Thompson
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3cc37e3f12
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Completely stripped down imperas simulation.
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
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2023-01-12 12:48:38 -06:00 |
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Ross Thompson
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2f2f3d6da5
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Stripped out all signature checking.
Removed multiple tests loop.
Only runs 1 test now.
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2023-01-12 12:45:44 -06:00 |
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Ross Thompson
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5ad0bacf5b
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Created separate imperas testbench.
Resolved logger issue with the duplicated instructions after commit.
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2023-01-12 12:07:07 -06:00 |
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Ross Thompson
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94f24d3f58
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Added instruction logger.
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2023-01-12 10:09:34 -06:00 |
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Katherine Parry
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77a982c977
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cleaned up all FPU files except for division
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2023-01-11 22:02:30 -06:00 |
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Ross Thompson
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6a616617d1
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Restored to default configuration.
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2023-01-09 00:21:45 -06:00 |
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Ross Thompson
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bf08c57ab0
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Added branch outcome logger to testbench
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2023-01-07 13:16:57 -06:00 |
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Ross Thompson
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f119b492bb
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2023-01-06 15:18:13 -06:00 |
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Ross Thompson
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7223d1e05c
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Added python script to post process performance counter metrics.
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2023-01-06 15:15:54 -06:00 |
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Ross Thompson
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09bb733088
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Added code to print out performance counters at end of each test.
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2023-01-05 18:00:11 -06:00 |
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Ross Thompson
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0eceeeeeaa
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Simiplified global history branch predictor.
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2023-01-04 23:41:55 -06:00 |
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Katherine Parry
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95a1ddd636
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some commenting fixes, converter optimizations, and moves normshift into postproc
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2023-01-03 15:55:30 -06:00 |
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Katherine Parry
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aca6f0d4e6
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removed ethe second bit from fma alignment shift
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2022-12-30 12:07:44 -06:00 |
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Katherine Parry
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5844a596a3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-30 09:56:35 -06:00 |
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David Harris
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e9b314f902
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fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression
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2022-12-30 06:40:25 -08:00 |
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Katherine Parry
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90eb4fc1f1
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minor optimizations and renaming
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2022-12-29 15:54:17 -06:00 |
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Katherine Parry
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1b4fa38510
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one bitt removed from inital lignment shift
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2022-12-28 17:46:53 -06:00 |
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Cedar Turek
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4ed2c6255c
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idiv passing radix 2, four copies
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2022-12-27 22:10:48 -08:00 |
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David Harris
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87abed6722
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cleanup
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2022-12-27 21:29:36 -08:00 |
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David Harris
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6cf73cdaee
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Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M
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2022-12-27 21:24:38 -08:00 |
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David Harris
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2de66e9eef
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Moved fdivsqrtexpcalc to its own file
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2022-12-26 08:45:43 -08:00 |
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David Harris
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7e77a39d32
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Restored missing floating point load/store tests
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2022-12-25 22:28:14 -08:00 |
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Katherine Parry
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4b50ffac91
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reworked negitive sticky bit handeling in fma
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2022-12-23 17:01:34 -06:00 |
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Ross Thompson
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98b824c4c4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-22 22:51:33 -06:00 |
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Ross Thompson
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206bc7daa6
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Closing in on icache flushed by FlushD rather than TrapM.
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2022-12-22 20:19:09 -06:00 |
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Kip Macsai-Goren
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a768d70093
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Added status.tvm bit test that passes make and regression
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2022-12-22 14:43:22 -08:00 |
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David Harris
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8bc753a291
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Added assertion about atomics needing caches
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2022-12-21 13:57:28 -08:00 |
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Ross Thompson
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3d95aa3423
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Added timeout check to testbench.
A watchdog checks the value of PCW. If it does not change within 1M cycles immediately stop simulation and report an error.
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2022-12-21 09:18:00 -06:00 |
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Ross Thompson
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376b01fcb8
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Attempted to make a cache test.
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2022-12-18 17:15:08 -06:00 |
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Ross Thompson
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ebdac1a9d0
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Updated tests for fpga and BP.
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2022-12-18 16:24:26 -06:00 |
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David Harris
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2457448e29
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Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
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2022-12-15 08:23:34 -08:00 |
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cturek
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f57211bb49
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Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs
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2022-12-10 21:56:35 +00:00 |
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Kip Macsai-Goren
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f486a763d9
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Addded fix for 32 bit periph test and added test to regression
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2022-12-06 09:56:08 -08:00 |
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Kip Macsai-Goren
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2dfa426e10
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added passing GPIO test to 64 bit tests
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2022-12-05 21:31:00 -08:00 |
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