Ross Thompson
7f12c7af90
Switch to use RV64IC for the benchmarks.
...
Still not working correctly with the icache.
instr
addr correct got
2021-04-07 19:12:43 -05:00
Ross Thompson
d901cfc848
Merge branch 'icache_bp_bug' into tests
...
Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Ross Thompson
a5dc175ab2
Merge remote-tracking branch 'refs/remotes/origin/tests' into tests
2021-04-06 21:20:55 -05:00
Ross Thompson
0a20e33971
Steps to getting branch predictor benchmarks running.
2021-04-06 21:20:51 -05:00
Jarred Allen
4da2688c40
Fix another bug in icache
2021-04-06 17:47:00 -04:00
Jarred Allen
ecb2bc8163
Fix another bug in icache
2021-04-06 12:48:42 -04:00
Jarred Allen
4ebc991a65
Fix bug in icache
2021-04-03 18:10:54 -04:00
Shreya Sanghai
bf3f4ff5b2
fixed minor bugs in localHistory
2021-04-01 13:40:08 -04:00
ShreyaSanghai
e33007e30e
added localHistoryPredictor
2021-04-01 22:22:40 +05:30
Shreya Sanghai
65e9747752
fixed bugs in global history to read latest GHRE
2021-03-31 21:56:14 -04:00
Ross Thompson
f1107c5d7b
Corrected a number of bugs in the branch predictor.
...
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
Ross Thompson
1e83810450
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Ross Thompson
a3925505bf
fixed some bugs with the RAS.
2021-03-30 13:57:40 -05:00
Jarred Allen
dd0b3fde59
Comment out failing tests
2021-03-30 13:07:26 -04:00
Jarred Allen
335178a1d3
Merge branch 'cache' into main
2021-03-30 12:56:19 -04:00
Jarred Allen
85164c7a87
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/regression/wave-dos/ahb-waves.do
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-busybear.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 12:55:01 -04:00
David Harris
9f0a58e193
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-26 13:04:52 -04:00
David Harris
aa0d0d50d8
Added fp test to testbench
2021-03-26 13:03:23 -04:00
Noah Boorstin
606295db2f
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/testbench/testbench-busybear.sv
2021-03-26 12:26:30 -04:00
Shreya Sanghai
edaf89e3d1
Merge branch 'PPA' into main
...
Conflicts:
wally-pipelined/testbench/testbench-privileged.sv
2021-03-25 20:35:21 -04:00
Shreya Sanghai
d3e914f64b
removed minor bugs
2021-03-25 20:29:50 -04:00
ShreyaSanghai
da4086db79
Removed PCW and InstrW from ifu
2021-03-26 01:53:19 +05:30
Noah Boorstin
ee3a53de7a
regression: use busybear batch instead
2021-03-25 15:34:10 -04:00
Domenico Ottolia
9e9fe5e9d3
More bug fixes for privileged tests
2021-03-25 15:05:55 -04:00
Noah Boorstin
9eb1786fb1
busybear: quick fix to mem reading
...
also stop ignoring mcause at the start
2021-03-25 14:29:11 -04:00
Brett Mathis
aedc96cd04
FPU Pipeline completed - can begin integration
2021-03-25 13:29:03 -05:00
Domenico Ottolia
fb00d0f209
Fix bugs with privileged tests
2021-03-25 14:06:05 -04:00
Noah Boorstin
ed37e933e5
busybear: stop NOPing out atomics
...
and bump regression to check for 800k instrs, up from 200k
2021-03-25 13:29:56 -04:00
David Harris
dea2ec280e
testgen-PIPELINE python startup
2021-03-25 13:12:18 -04:00
Shriya Nadgauda
e55a245948
adding PIPELINE tests
2021-03-25 13:07:25 -04:00
Jarred Allen
abedaf62a8
Output NOP instead of BAD when reset
2021-03-25 12:42:48 -04:00
Jarred Allen
2f5d854f87
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/src/uncore/dtim.sv
2021-03-25 12:10:26 -04:00
Teo Ene
7c3963547d
Config file for ppa experiments
2021-03-25 10:23:21 -05:00
David Harris
1158b3aa73
Added PPA README
2021-03-25 11:21:31 -04:00
Thomas Fleming
89a2fe5741
Finish finite state machines for page table walker
2021-03-25 02:48:40 -04:00
Thomas Fleming
4f01aae844
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-25 02:35:21 -04:00
bbracker
d52c71086a
added 1 tick delay to dtim flops
2021-03-25 02:23:30 -04:00
bbracker
ca392225df
added 1 tick delay on tim reads
2021-03-25 02:15:28 -04:00
Jarred Allen
9cbdb44728
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/src/ifu/ifu.sv
2021-03-25 00:51:12 -04:00
bbracker
6edb055f26
instrfault direspecting stalls bugfix
2021-03-25 00:44:35 -04:00
bbracker
5327dcfcc8
instrfaults not respecting stalls bugfix
2021-03-25 00:16:26 -04:00
bbracker
a8b7d7a248
upgraded gpio bus interface
2021-03-25 00:15:02 -04:00
bbracker
3e656fc035
future work comment about suspicious-looking verilog in csri.sv
2021-03-25 00:10:44 -04:00
Thomas Fleming
f2604797fb
Add all PMP addr registers
2021-03-24 21:58:33 -04:00
Teo Ene
1e691e120b
Fix typo from last commit
2021-03-24 17:09:58 -05:00
Teo Ene
9f44eb36ef
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-24 17:04:48 -05:00
Teo Ene
6a7b69ff2d
Updated coremark_bare testbench for IM
2021-03-24 17:04:43 -05:00
Katherine Parry
123e63b440
fixed various bugs in the FMA
2021-03-24 21:51:17 +00:00
Teo Ene
07f7df82e3
Added BPTYPE to coremark_bare config
2021-03-24 16:38:29 -05:00
Ross Thompson
cdb7d15709
Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
2021-03-24 15:56:55 -05:00
