Ross Thompson
eb19b1b499
Imperas found a bug with the Fence.I instruction.
...
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold. This cause the d$ flush to go high while in ReadHold. The solution is
to ensure the cache continues to assert Stall while in WriteLine state.
There was a second issue also. The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
2023-01-20 10:17:21 -06:00
David Harris
364cf97c34
cache cleanup
2023-01-14 19:43:29 -08:00
David Harris
7d93659f6b
changed name to CORE-V-WALLY
2023-01-11 15:15:08 -08:00
David Harris
b911056e66
Changed Wally to CORE-V Wally
2023-01-11 14:03:44 -08:00
David Harris
e92cffbb5e
Changed MIT license to Solderpad License
2023-01-10 11:35:20 -08:00
Ross Thompson
693f32973f
Minor optimizations.
2022-12-23 20:11:36 -06:00
Ross Thompson
b3ff4fe02e
CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled.
2022-12-21 22:13:05 -06:00
Ross Thompson
d1aa5ba890
Updated cache fsm names to match book.
2022-12-21 16:49:53 -06:00
Ross Thompson
5acdf541b9
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
c985988867
Fixed a bug with the new cache flush changes.
2022-12-16 19:28:32 -06:00
Ross Thompson
5f556817c7
Further cleanfsm cleanup.
2022-12-16 16:37:45 -06:00
Ross Thompson
493b1a4280
More cachefsm cache flush cleanup.
2022-12-16 16:32:21 -06:00
Ross Thompson
3132246a46
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
91e64a0d67
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
ab3c5a0ca7
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
Ross Thompson
4a0e4aed99
Signal renames to reflect figures.
2022-12-14 09:49:15 -06:00
Ross Thompson
232f866ad1
Renamed CPUBusy to Stall in cache.
2022-12-11 15:49:34 -06:00
Ross Thompson
1a9c932157
Renamed SelBusBuffer to SelFetchBuffer.
2022-12-05 17:51:13 -06:00
Ross Thompson
dc31add951
Cache signal renames.
2022-12-04 16:09:09 -06:00
Ross Thompson
5025664cb0
Removed unused port on cacheway.
2022-12-01 11:47:48 -06:00
Ross Thompson
cedb234013
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
2022-11-30 11:01:25 -06:00
Ross Thompson
78acd40424
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
b53f8eceef
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
Ross Thompson
44171c342d
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
Ross Thompson
6696624971
comment updates.
2022-10-22 16:28:44 -05:00
Ross Thompson
494f8b94f4
Reordered the eviction and fetch in cache so it follows a more logical order.
2022-10-04 17:36:07 -05:00
Ross Thompson
4062fe56c0
Possible fix to the bus cache interaction.
2022-09-27 11:34:33 -05:00
Ross Thompson
07bb11518e
Found a hidden bug in the cache to bus fsm interlock.
2022-09-26 17:41:30 -05:00
Ross Thompson
0fcc314d06
Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
2022-09-26 12:48:26 -05:00
Ross Thompson
38edbde966
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
...
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
2022-09-23 11:46:53 -05:00
Ross Thompson
2c86badeb2
pipelining of fetch into evict AHB requests.
2022-09-13 17:51:55 -05:00
Ross Thompson
5409501ca6
Maybe fixed it?
2022-08-30 18:08:34 -05:00
Ross Thompson
637d60b64c
Progress.
2022-08-30 14:17:00 -05:00
Ross Thompson
ebe4339953
Updated fpga test bench.
...
Solved read delay cache bug. Introduced during cache optimizations.
2022-08-21 15:59:54 -05:00
Ross Thompson
85dbec5969
Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.
2022-08-21 15:28:29 -05:00
Ross Thompson
2ba390adf4
Possible reduction of ignorerequest.
2022-08-19 18:07:44 -05:00
Ross Thompson
719b00e338
Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
2022-07-24 01:20:29 -05:00
Ross Thompson
69d520a7eb
Removed replay from the config files.
2022-07-24 00:34:11 -05:00
Ross Thompson
cd68896637
Merged evict dirty clear with flush write back.
2022-07-24 00:22:43 -05:00
Ross Thompson
27e32980ad
cache cleanup after removing replay on cpubusy.
2022-07-22 23:30:25 -05:00
Ross Thompson
17ae1a1b1b
cache fsm cleanup after removal of replay.
2022-07-22 23:25:09 -05:00
Ross Thompson
abc79c6c8e
Possible improvement to cache which removes the cpu_busy states.
2022-07-22 23:20:37 -05:00
Ross Thompson
1cad05fef9
Minor cleanup of cache.
2022-07-19 23:04:23 -05:00
Ross Thompson
8698799077
Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
2022-07-19 22:42:25 -05:00
Ross Thompson
a79e5e11f6
Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
2022-07-18 23:37:18 -05:00
Ross Thompson
ab9738d3be
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
60e6c1ffa7
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
Ross Thompson
1e7e59bdbd
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
f87a6f2c63
More cache cleanup.
2022-02-13 12:38:39 -06:00
