Ross Thompson
7d00649b61
Formating changes to cache fsms.
2021-12-13 17:16:13 -06:00
Ross Thompson
5361f69639
Fixed some typos in the dcache ptw interaction documentation.
2021-12-13 15:47:20 -06:00
Ross Thompson
8e39034dbd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-12 17:33:29 -06:00
Ross Thompson
2f282e5570
Revert "Privilige .*s removed"
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This reverts commit 471f267987
2021-12-12 17:31:57 -06:00
Ross Thompson
fdbb7b6ef3
Revert "Priviledged .* removed"
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This reverts commit 96ac298596
2021-12-12 17:31:39 -06:00
Ross Thompson
547093b705
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-12 17:21:51 -06:00
Ross Thompson
bb79f70a63
Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
2021-12-12 17:21:44 -06:00
Ross Thompson
e6f2a316c8
Missed constraints file for xilinx ILA.
2021-12-12 15:06:29 -06:00
Ross Thompson
b88ec949cf
Added proper credit to Richard Davis, the author of the original sd card reader.
2021-12-12 15:05:50 -06:00
kwan
96ac298596
Priviledged .* removed
2021-12-12 09:55:45 -08:00
kwan
471f267987
Privilige .*s removed
2021-12-12 09:54:14 -08:00
Kevin
78fbe542a9
edited one testbench, yet to run regression
2021-12-10 20:26:20 -08:00
Ross Thompson
c688b27a20
Performance counters now output of coremark.
2021-12-09 14:48:17 -06:00
Ross Thompson
cd59809e42
Fixed numerous errors in the preformance counter updates.
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Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
2021-12-09 11:44:12 -06:00
bbracker
4bc4930ff3
fix recursive signal logging for graphical sims
2021-12-08 16:07:26 -08:00
bbracker
64652be7c5
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 14:12:18 -08:00
bbracker
c97e96f553
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 14:12:09 -08:00
bbracker
6a6835ddc3
fix release of ReadDataM
2021-12-08 14:11:43 -08:00
slmnemo
3ff994f50d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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help
2021-12-08 14:09:58 -08:00
slmnemo
094f45e28b
Removed .* from /wally-pipelined/src/uncore/uart.sv
2021-12-08 14:02:53 -08:00
Ross Thompson
a55018b67a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-08 15:50:43 -06:00
Ross Thompson
3bdda9687a
Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict.
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Remove preload from dtim.
2021-12-08 15:50:15 -06:00
Noah Limpert
e97dd080a0
updated fcmp.sv instantiation to remove x*'s
2021-12-08 13:34:33 -08:00
Ross Thompson
37451b8978
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-08 13:40:44 -06:00
Ross Thompson
e1249f4312
Updated coremark testbench with the extra ports from FPGA merge.
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Fixed coremark Makefile to create work directory.
2021-12-08 13:40:32 -06:00
bbracker
4060e77b56
increase regression's expectations of buildroot to 246 million
2021-12-08 07:01:22 -08:00
slmnemo
d58f318d39
Removed .*s from wally-pipelined/src/uncore/uncore.sv
2021-12-08 01:03:02 -08:00
slmnemo
52b4802600
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 00:26:13 -08:00
Noah Limpert
feb21d1c4a
removed .* instantiation from ieu.sv and datapth.sv in ieu folder
2021-12-08 00:24:27 -08:00
slmnemo
acacd13ffc
Removed .* from mmu instance inside lsu.sv.
2021-12-08 00:15:30 -08:00
Katherine Parry
d0e708f239
FMA uses one LOA
2021-12-07 14:15:43 -08:00
bbracker
d459e35645
undo intentionally breaking commit
2021-12-07 13:43:47 -08:00
bbracker
3379b74bb2
intentionally breaking commit
2021-12-07 13:27:34 -08:00
bbracker
cf61187273
undo intentionally breaking commit
2021-12-07 13:27:06 -08:00
bbracker
69f025a642
intentionally breaking commit
2021-12-07 13:23:19 -08:00
bbracker
ec6c3bd74c
2nd attempt at making regression-wally.py able to be run from a different dir
2021-12-07 13:13:30 -08:00
bbracker
0c48725fa5
fix checkpointing so that it can find the synchronized reset signal
2021-12-07 13:12:06 -08:00
bbracker
9fc4f3bfef
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-07 11:16:51 -08:00
bbracker
0692372037
attempt to make regression-wally.py more path-independent such that git bisect can invoke it directly
2021-12-07 11:16:43 -08:00
Ross Thompson
51e2b9ea6f
Added information on how to copy the linux image to flash card.
2021-12-07 13:16:38 -06:00
bbracker
8e2a9d5bbb
add buildroot tv linking to make-tests.sh
2021-12-07 11:15:59 -08:00
Ross Thompson
c7be8a701e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-07 13:12:59 -06:00
Ross Thompson
8bb3d51aad
Added generate around the dtim preload.
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Added readme to explain FPGA.
2021-12-07 13:12:47 -06:00
Ross Thompson
3d829dbbd3
Fixed two issues.
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First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
bbracker
ffe7cf83e5
regression.py bugfix
2021-12-06 19:32:38 -08:00
bbracker
b714490f92
add make-tests scripts
2021-12-06 15:37:33 -08:00
bbracker
d702599d56
add buildroot-only option to regression
2021-12-06 14:13:58 -08:00
bbracker
6c9db52801
linux-testvectors symlinks shouldn't be in repo, especially not in this location
2021-12-05 22:03:51 -08:00
Ross Thompson
517cae796c
Fixed more constraint issues in fpga.
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Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
David Harris
19fb0aace8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-04 20:26:01 -08:00
