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Author SHA1 Message Date
Alec Vercruysse
7ba2bfd4b6 CacheFSM logic simplification for AMO operations 
Ran this by Ross.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
b52512b1ae D$ scope-specific coverage exclusions (I$ logic that never fires) 
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.

Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.

There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
3de03abd9d add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd9feb0260 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
e3593800d9 fix unhit exclusion in fdivsqrtfsm 2023-04-19 01:34:01 -07:00
David Harris
d5e2fefe2c
Merge pull request #252 from mcook26/main 
Increase of TLB coverage in IFU
 2023-04-18 05:49:18 -07:00
Miles Cook
5cfd0577d1 Increase of TLB coverage in IFU 2023-04-17 18:35:03 -07:00
David Harris
bdd5f5e611
Merge pull request #251 from masonadams25/main 
Removed redundent expression to increase coverage
 2023-04-17 12:37:27 -07:00
Ross Thompson
981fcc6f4a
Merge pull request #249 from davidharrishmc/dev 
DV Test Plan, fdivsqrt, merged exclusions
 2023-04-17 14:32:37 -05:00
Mason Adams
4468086e06
Removed redundent expression to increase coverage 2023-04-17 14:13:26 -05:00
David Harris
d327ed494a Started DV Test Plan 2023-04-17 10:18:06 -07:00
David Harris
b00b8ba366 merged coverage exclusions 2023-04-17 10:17:48 -07:00
David Harris
171fc0ee7f
Merge pull request #248 from dherreravicioso/main 
Added test coverage for reads to HPM counters and coverage exclusions
 2023-04-16 18:18:31 -07:00
Diego Herrera Vicioso
34dd481f93 Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc 2023-04-15 23:13:39 -07:00
Ross Thompson
a77d403e4c
Merge pull request #233 from AlecVercruysse/coverage3 
Full I$ coverage
 2023-04-14 22:15:11 -05:00
Alec Vercruysse
862d1e0116 replace instances of code duplication for i$ exclusions w/commands 2023-04-14 17:10:39 -07:00
Ross Thompson
29146ac839
Merge pull request #247 from AlecVercruysse/code_quality 
Code Quality
 2023-04-14 16:46:39 -05:00
Limnanthes Serafini
5952a4b0a3 Final small fix 2023-04-14 14:15:52 -07:00
Limnanthes Serafini
e20f00a520 Merge branch 'code_quality' of https://github.com/AlecVercruysse/cvw into code_quality 2023-04-14 14:14:40 -07:00
Limnanthes Serafini
34aedc4f79 indent fix 2023-04-14 14:14:34 -07:00
Limnanthes Serafini
1b8e9cd9ac
Merge branch 'openhwgroup:main' into code_quality 2023-04-14 14:13:15 -07:00
David Harris
afd2cc9c91 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-14 12:57:26 -07:00
Ross Thompson
1a77bd7554
Merge pull request #245 from Dygore/main 
Added Multiple tests to increase FPU Coverage
 2023-04-14 14:51:28 -05:00
Dylan
8ee76174d7
Merge branch 'openhwgroup:main' into main 2023-04-14 14:41:26 -05:00
Dygore
92a0827d80 Added multiple tests to increase FPU coverage 2023-04-14 14:41:05 -05:00
David Harris
f77fee605f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-14 04:16:11 -07:00
David Harris
e8d630d069
Merge pull request #244 from Dygore/main 
Added tests for full coverage of the FPU result sign module
 2023-04-14 04:02:29 -07:00
Dylan
4c91bb3b76
Merge branch 'openhwgroup:main' into main 2023-04-14 00:36:57 -05:00
Dygore
23dbca3991 Added tests for full coverage of the FPU result sign module 2023-04-14 00:36:12 -05:00
Limnanthes Serafini
95223bf11c More cleanup 2023-04-13 21:34:50 -07:00
Limnanthes Serafini
28dd41291a More cleanup 2023-04-13 21:02:30 -07:00
Limnanthes Serafini
94b686fcf6 More changes 2023-04-13 21:02:15 -07:00
Limnanthes Serafini
5d12afa671 Some cleanup 2023-04-13 21:01:57 -07:00
Limnanthes Serafini
4ec28ef32d
Merge branch 'openhwgroup:main' into code_quality 2023-04-13 19:59:58 -07:00
Limnanthes Serafini
6fddc591b5 Finished up testbench reformatting 2023-04-13 19:18:26 -07:00
Limnanthes Serafini
99cd913d75 Further indents 2023-04-13 19:07:43 -07:00
Limnanthes Serafini
0862688168 testbench code visual improvements 2023-04-13 19:06:09 -07:00
David Harris
cfca584bc7 Merged coverage-exclusions 2023-04-13 18:15:23 -07:00
David Harris
fe083e1edc
Merge pull request #243 from Noah-G-L/main 
Pull Request to add tlbKP.S - Fill in cache lines
 2023-04-13 18:13:04 -07:00
Noah Limpert
30ed9c2b69 add back K. Box and M. Cook Lsu test 2023-04-13 17:50:18 -07:00
Noah Limpert
187c5b07c7 make pull request more clean 2023-04-13 17:44:09 -07:00
Noah Limpert
c76de00d60 Revert "instantiate 5 4KiB arrays, aim to thrash all 4 ways" 
This reverts commit 0fea40282a.
 2023-04-13 17:40:39 -07:00
David Harris
2e568877b0 fdivsqrtfsm coverage attempt to waive a state 2023-04-13 17:40:14 -07:00
Noah Limpert
4ab27b4f12 Revert "Test File for Pull Request, Attempt to fill all four ways" 
This reverts commit f770243689.
 2023-04-13 17:28:37 -07:00
David Harris
b378001213
Merge pull request #237 from SydRiley/main 
fctrl coverage at 100% after removing redundancies from conditionals
 2023-04-13 17:10:46 -07:00
David Harris
1c9c94563d
Merge pull request #242 from AlecVercruysse/cachesim 
InvalDelayed warning fix; Miscellaneous typo and indent cleanup
 2023-04-13 17:07:47 -07:00
Noah Limpert
bcbbcd5a30 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-13 17:00:48 -07:00
Limnanthes Serafini
38349e6a4f Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 17:00:43 -07:00
Limnanthes Serafini
51f6561476 A couple indents->spaces 2023-04-13 17:00:41 -07:00
Noah Limpert
419377a8f8 git did not seem to add tests.vh, trying again 2023-04-13 16:59:10 -07:00