David Harris
e700e404c9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 17:29:01 -05:00
David Harris
9a51bb27c3
Implemented adrdec for uncore
2021-01-29 17:28:53 -05:00
Teo Ene
9eafdbe349
- Removed latch on CSRCReadValM in csrc.sv
...
- Changed top level to wallypipelinedhart
2021-01-29 15:56:51 -06:00
Teo Ene
8679e9aae3
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-01-29 15:04:51 -06:00
Teo Ene
94b35ac47c
Synth automatically globs all available verilog files now, instead of requiring manual file listing
2021-01-29 15:04:43 -06:00
David Harris
8d4f5277d2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 15:38:01 -05:00
David Harris
dc2443c55b
Moving data memory to uncore
2021-01-29 15:37:51 -05:00
Teo Ene
3d02d6f09f
Added AHBW to rv32ic config file as well
2021-01-29 12:29:08 -06:00
Noah Boorstin
194d5b55ab
update busybear testbench to conform to new structure
2021-01-29 17:46:50 +00:00
David Harris
a94c09cad8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 01:07:22 -05:00
David Harris
ed3cb83c10
Added ahblite bus interface unit
2021-01-29 01:07:17 -05:00
Noah Boorstin
dabb026104
busybear: lie about MISA to match OVP's MISA
2021-01-29 00:58:56 -05:00
Noah Boorstin
8ab5879af5
busybear testbench: test on first 100k instrs
...
currently gets about 47k instrs correctly
also fix gdb parsing to avoid accidently matching on function names
2021-01-29 00:14:23 -05:00
David Harris
618c6e4813
Renamed modules in privileged unit
2021-01-28 23:21:12 -05:00
David Harris
fd2f854a69
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-28 21:40:57 -05:00
David Harris
05b755958f
Hint to optimize ifu
2021-01-28 21:40:48 -05:00
Noah Boorstin
619dec1490
busybear: simulate first 10k instructions
...
I know we need to add CSR checking sometime soon
Also I'm a bit sketpical this is all working properly, and that no new bugs
were uncovered from 1k instrs to 10k instrs
2021-01-28 19:44:58 -05:00
Noah Boorstin
4f84bd3c8f
busybear: fix misaligned writing checking
2021-01-28 19:35:09 -05:00
Noah Boorstin
beb93e2508
busybear: add more test instructions
...
currently testing first 1k instrs
2021-01-28 16:41:37 -05:00
Noah Boorstin
287cf4e5a6
oops forgot to add C.BEQZ, C.BNEZ checks to busybear testbench
2021-01-28 16:35:12 -05:00
Noah Boorstin
91e9defd0a
more of the same fixes
2021-01-28 16:26:15 -05:00
Noah Boorstin
623d9feeab
more misaligned read fixing
...
I'm getting fairly concerned about this, I feel like
this should only work if the memory ignores the lower 3 or 4 bits of the adr
2021-01-28 16:14:35 -05:00
David Harris
12c6006f07
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-28 15:44:14 -05:00
David Harris
fe0876027f
Fixed floating signals in clint and ieu
2021-01-28 15:44:05 -05:00
Noah Boorstin
405c9d90b5
busybear testbench: understand bytemask for writes
2021-01-28 15:42:47 -05:00
Noah Boorstin
7a3f29b260
Make gdb output parser understand other varients of load/store
2021-01-28 15:35:41 -05:00
David Harris
ad5d4793b6
Fixed c.jr instruction improperly writing ra
2021-01-28 15:18:23 -05:00
Noah Boorstin
a4bac85ece
busybear: ret is only 1 word
2021-01-28 14:47:40 -05:00
Noah Boorstin
0befdfacec
add speculative exception for compressed instructions
2021-01-28 14:40:35 -05:00
Noah Boorstin
27142f0fef
testbench now understands lw not aligned to 8 bytes
...
also busybear now has first 500 instead of 100 instrs
and prints current instrs less
2021-01-28 13:33:22 -05:00
Noah Boorstin
a2598b2b30
busybear testbench: check for read data address also
...
and check for more end of files better
2021-01-28 13:16:38 -05:00
Noah Boorstin
f2aea55def
update busybear testbench to conform to new structure
2021-01-28 01:21:47 -05:00
Noah Boorstin
206747b8b2
Busybear test now processes first 100 instrs correctly!
...
- changed test parser to recognize lw in addition to lw
also, added temporary questa files (wlft*) to .gitignore
2021-01-28 01:19:27 -05:00
Noah Boorstin
8f6994196a
fix memory write address decoding for busybear tests
2021-01-28 01:19:26 -05:00
David Harris
f95d0690ca
Created DCU and moved memdp into DCU
2021-01-28 01:03:12 -05:00
David Harris
be1d1886a9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-28 00:22:11 -05:00
David Harris
a50b6c2a15
Provided PC + 2 or 4 (PCLink) for JAL
2021-01-28 00:22:05 -05:00
Noah Boorstin
28fabb94ee
update busybear testbench to conform to new structure
2021-01-27 23:42:19 -05:00
David Harris
4df461ad77
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-27 22:49:55 -05:00
David Harris
824014c5c0
Repartitioned with Instruction Fetch Unit, Integer Execution Unit
2021-01-27 22:49:47 -05:00
Noah Boorstin
c9baa70e26
update busybear testbench to conform to new structure
2021-01-27 12:54:09 -05:00
David Harris
616afaba69
Moved privileged unit from datapath to hart
2021-01-27 07:46:52 -05:00
David Harris
e84fbd0a73
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-27 06:40:39 -05:00
David Harris
b88508ca11
Repartitioned datapath and controller into ieu
2021-01-27 06:40:26 -05:00
Noah Boorstin
1195ebb468
show instruction assembly in waveform
2021-01-26 12:34:12 -05:00
Noah Boorstin
6c567aab9a
Update busybear tests to conform to new directory structure
2021-01-25 20:37:18 -05:00
Noah Boorstin
e92db93939
Fixed mem write checking
...
now passes around 50 instructions!
2021-01-25 20:07:08 -05:00
Noah Boorstin
358393a1da
fix speculation ignoring for PC fetching
2021-01-25 20:07:06 -05:00
David Harris
1d9c741c00
Reset Vector moved to config file
2021-01-25 15:57:36 -05:00
Teo Ene
4e0b13696b
Added synth and PnR flow
2021-01-25 14:28:14 -06:00
