Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
56 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
206747b8b2
Go to file
Noah Boorstin 206747b8b2 Busybear test now processes first 100 instrs correctly! 
- changed test parser to recognize lw in addition to lw

also, added temporary questa files (wlft*) to .gitignore
2021-01-28 01:19:27 -05:00
riscv-o3@a13ac64fa5 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
sky130 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
wally-pipelined Busybear test now processes first 100 instrs correctly! 2021-01-28 01:19:27 -05:00
.gitignore Busybear test now processes first 100 instrs correctly! 2021-01-28 01:19:27 -05:00
.gitmodules Added synth and PnR flow 2021-01-25 14:28:14 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor