Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
2,614 Commits 5 Branches 2 Tags 53 MiB
789cf13be6
Commit Graph

2614 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
David Harris
52b8b68086 Added math.h to fir.c 2022-01-28 00:26:06 +00:00
Ross Thompson
1bb8d36308 Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
Ross Thompson
d7d7c1cb7d Relocated the misalignment faults. 2022-01-27 16:03:00 -06:00
David Harris
87aa0724a2 IFU cleanup 2022-01-27 17:18:55 +00:00
David Harris
218ff3e25d IFU cleanup 2022-01-27 16:41:57 +00:00
David Harris
1c22077841 Optimized out second adder from IFU for PC+2 2022-01-27 16:06:24 +00:00
David Harris
62e5c7fd13 Comments in LSU code about restructuring 2022-01-27 15:53:59 +00:00
Ross Thompson
9a9dfcae40 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-27 08:45:33 -06:00
Ross Thompson
d38ab9d2d7 Increased number of concurrent tests. 2022-01-27 08:45:25 -06:00
David Harris
975c0e72c8 Set up rv32emc config 2022-01-27 14:37:58 +00:00
David Harris
5eccbcf531 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-27 14:33:35 +00:00
David Harris
384cd0d092 Added synthesis submodules 2022-01-27 14:31:34 +00:00
Ross Thompson
aa474ad588 Added generated source code for the wally riscv arch tests rv32i_m and rv64i_m. 2022-01-27 08:11:46 -06:00
Ross Thompson
75c33bc6c9 BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush. 2022-01-27 07:59:59 -06:00
Ross Thompson
b961b104e0 Added colors to regression script to make it easy to pick out success from fail. 2022-01-26 22:40:32 -06:00
Ross Thompson
c3a78553be Removed mux in PCNextF logic. Minor IFU improvements. 2022-01-26 22:33:26 -06:00
Ross Thompson
23c4ba2777 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. 
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
 2022-01-26 18:23:39 -06:00
Ross Thompson
2c982dca03 IFU simplifications. 2022-01-26 13:54:59 -06:00
David Harris
0023c4cb57 Adjusted test cases for new GPIO base address 2022-01-26 19:15:48 +00:00
David Harris
c6adb7b6b1 Updated configs to fix GPIO address to match FU540 2022-01-26 18:16:34 +00:00
David Harris
c60bb68bff Testgen working for Lab 2 2022-01-26 18:01:51 +00:00
David Harris
492c1a488e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-26 17:21:09 +00:00
David Harris
f90e58ff34 New testgen.py 2022-01-26 17:21:02 +00:00
bbracker
ea92cc3af2 a different approach to QEMU: add Wally as a completely new machine 2022-01-26 15:02:24 +00:00
Ross Thompson
728e46a794 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-25 19:21:04 -06:00
Ross Thompson
db197b6491 Added pin location for reset on VCU118 board. Somehow this was missing and still worked. 2022-01-25 17:48:42 -06:00
David Harris
1e533cdf25 Removed and restored embench-iot 2022-01-25 22:12:28 +00:00
Ross Thompson
71eb1df492 Added comport.setup to remind how to configure com port for xilinx fpga. 
Added load-deadlock.tsm to trigger load operation deadlock.
 2022-01-25 14:54:38 -06:00
David Harris
22c84dcd80 simpleram simplification 2022-01-25 19:46:13 +00:00
David Harris
8bf73d0eb3 simpleram simplification 2022-01-25 19:40:07 +00:00
David Harris
f07123ff0f simpleram simplification 2022-01-25 18:26:31 +00:00
David Harris
7ac44cb3fc simpleram address simplification 2022-01-25 18:17:33 +00:00
David Harris
5eb71a3bbe simpleram address simplification 2022-01-25 18:00:50 +00:00
David Harris
d9888c91a6 simpleram clk and reset simplification 2022-01-25 17:34:15 +00:00
David Harris
5cb879129e Start of IFU cleanup 2022-01-25 17:31:53 +00:00
David Harris
0660e5fe51 removed sum executable 2022-01-25 10:24:05 +00:00
David Harris
44c58cfa20 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-25 06:53:07 +00:00
David Harris
4c8c359894 More example Makefile cleanup 2022-01-25 06:53:03 +00:00
davidharrishmc
6fa63bf6d7 Update README.md 2022-01-24 15:47:42 -08:00
davidharrishmc
edff52c692 Update README.md 2022-01-24 15:46:24 -08:00
David Harris
96e9cd6ef1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-24 23:21:16 +00:00
David Harris
26013a984b Fixed sumtest reference output; added embench benchmark directory 2022-01-24 23:21:09 +00:00
kaveh Pezeshki
3314fb48c4 added qemu patches in tests/linux-testgen/qemu 2022-01-24 07:52:07 +00:00
Ross Thompson
4d4d9ac8cf Added spill support back into the IROM IFU. 2022-01-21 15:50:54 -06:00
Ross Thompson
4ecc2d029a Changed the IROM and DTIM memories to behave like edge-triggered srams. 2022-01-21 15:42:54 -06:00
David Harris
c2c7351b24 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-21 00:12:18 +00:00
David Harris
0bb63e9ad1 Fixed path to riscvOVPsimPlus 2022-01-21 00:12:14 +00:00
Ross Thompson
ec44774c77 Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv 2022-01-20 16:39:54 -06:00
David Harris
d1162eeebf fir.c 2022-01-20 17:15:53 +00:00
David Harris
ac28880cd9 Added FIR example 2022-01-20 16:57:36 +00:00