32 Commits

Author	SHA1	Message	Date
Thomas Fleming	4b2765f8e2	Complete basic page table walker	2021-03-30 22:19:27 -04:00
Thomas Fleming	89a2fe5741	Finish finite state machines for page table walker	2021-03-25 02:48:40 -04:00
Thomas Fleming	4f01aae844	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-25 02:35:21 -04:00
bbracker	5327dcfcc8	instrfaults not respecting stalls bugfix	2021-03-25 00:16:26 -04:00
bbracker	3e656fc035	future work comment about suspicious-looking verilog in csri.sv	2021-03-25 00:10:44 -04:00
Thomas Fleming	f2604797fb	Add all PMP addr registers	2021-03-24 21:58:33 -04:00
Shreya Sanghai	09b90557f7	PC counts branch instructions	2021-03-23 14:25:51 -04:00
Shreya Sanghai	dfc86539cc	Merge branch 'gshare' into main ... Conflicts: wally-pipelined/regression/wave.do	2021-03-18 17:25:48 -04:00
Thomas Fleming	859d242d81	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-18 14:36:42 -04:00
Thomas Fleming	062c4d40da	Connect tlb, pagetablewalker, and memory	2021-03-18 14:35:46 -04:00
Noah Boorstin	847bf0b9a6	change ifndef to generate/if	2021-03-18 12:50:19 -04:00
Shreya Sanghai	23a7c8cd92	made performance counters count branch misprediction	2021-03-16 11:24:17 -04:00
Shreya Sanghai	518618ad38	Merge branch 'counters' into main ... added a configurable number of performance counters	2021-03-16 11:01:30 -04:00
Thomas Fleming	ca2a65770c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-05 15:46:51 -05:00
Thomas Fleming	e48dc38869	Export SATP_REGW from csrs to MMU modules	2021-03-05 01:22:53 -05:00
Noah Boorstin	0af002eb2f	busybear: make CSRs only weird for us	2021-03-05 00:46:32 +00:00
Shreya Sanghai	f95a1eadd9	fixed bugs	2021-03-04 12:59:45 -05:00
Shreya Sanghai	7cd8f1a592	added performance counters	2021-03-04 11:42:52 -05:00
Noah Boorstin	a267115635	Merge branch 'main' into busybear	2021-02-28 20:45:08 +00:00
Noah Boorstin	856a1079cc	busybear: change sstatus, mstatus reset value	2021-02-28 16:19:03 +00:00
David Harris	73920282af	Eliminated flushing pipeline on CSR reads	2021-02-26 17:00:07 -05:00
David Harris	0258901865	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
kaveh pezeshki	e8b306bcba	merged with main to integrate with AHB	2021-02-26 05:37:10 -08:00
David Harris	7737b0f709	Fixed fetch stall after jump in bus unit	2021-02-23 09:08:57 -05:00
Noah Boorstin	43f9abdbed	busybear testbench: check (almost) all the CSRs	2021-02-16 20:03:24 -05:00
David Harris	cc42655789	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
Noah Boorstin	c03f69fb80	Change CSR reset and available bits to conform to OVPsim ... Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.	2021-02-04 22:03:45 +00:00
David Harris	756352f129	Minor tweaks	2021-02-02 19:44:37 -05:00
David Harris	429f48e766	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	bb83fda1d8	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	92bf1674b4	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00