17 Commits

Author	SHA1	Message	Date
Ross Thompson	7a824eaae1	Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.	2022-03-24 23:47:28 -05:00
Ross Thompson	2a8a1cd191	Minor cleanup to interlockfsm.	2022-03-08 23:38:58 -06:00
David Harris	48705457d5	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
Ross Thompson	90be3d4360	Clarified interlockfsm.	2022-02-22 11:31:28 -06:00
Ross Thompson	3a29504279	Added some clearity to lsuvirtmem.sv.	2022-02-21 17:20:58 -06:00
Ross Thompson	2f711fb642	Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.	2022-02-21 16:54:38 -06:00
Ross Thompson	0c65ea96d8	Cleaned up names in lsuvirtmem.	2022-02-21 16:44:30 -06:00
Ross Thompson	56fc6d0d7c	Minor cleanup of lsu.	2022-02-21 12:46:06 -06:00
Ross Thompson	f48b12b089	Moved mux into lsuvirtmem.	2022-02-21 09:31:29 -06:00
Ross Thompson	ae06785b9f	Minor changes to LSU.	2022-02-19 14:38:17 -06:00
Ross Thompson	6cd9d84e7f	New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.	2022-02-17 17:19:41 -06:00
Ross Thompson	0eec096474	Rough implementation passing regression test with hptw atomic writes to memory.	2022-02-17 14:46:11 -06:00
Ross Thompson	2fc7dc3e57	Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.	2022-02-17 10:04:18 -06:00
Ross Thompson	62f5f1e622	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
Ross Thompson	911ee36b22	Removed all possilbe paths to PreSelAdr from TrapM.	2022-02-09 19:20:10 -06:00
David Harris	c12407ba6a	Removed Busybear dependencies	2022-02-02 20:28:21 +00:00
Ross Thompson	7c3d6bbdb4	Moved lsu virtual memory logic into separate module.	2022-01-31 11:56:03 -06:00