Ross Thompson
705572f0ac
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
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If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
Ross Thompson
9c875d38a9
Fixed the 4 way set associative pseudo LRU replacement policy.
2021-10-29 12:46:02 -05:00
Ross Thompson
41dbb59e24
Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.
2021-10-29 11:03:37 -05:00
Ross Thompson
35fcadbe7f
Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.
2021-10-28 11:07:18 -05:00
Ross Thompson
c4170ece27
Replaced async reset flip flops with sync reset flip flops in cache and bpread.
2021-10-27 09:57:11 -05:00
David Harris
426a43f77b
Forgot to save cacheway merge
2021-10-26 08:38:13 -07:00
David Harris
c0145c0a35
merging changes
2021-10-26 08:34:36 -07:00
David Harris
8287a1ef3e
Synchronous reset in non-flop blocks
2021-10-26 08:30:35 -07:00
Ross Thompson
c43b19120f
Fixed another critical path in the caches.
2021-10-25 22:05:11 -05:00
Ross Thompson
1228dbbebc
Fixed the timing issue in the cache replacement polcy.
2021-10-25 18:00:23 -05:00
Ross Thompson
576383c74b
Fixed bug with the changes to sram1rw.
2021-10-25 16:11:41 -05:00
Ross Thompson
5fd3f7f2c7
Possible fix for critical path timing in caches.
2021-10-25 15:33:33 -05:00
Ross Thompson
76bba541a7
Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.
2021-10-24 21:21:49 -05:00
Ross Thompson
8a51fe76c1
Partial cleanup of unused signals in caches and bpred.
2021-10-24 15:04:20 -05:00
David Harris
c9e9cd4a60
more lsu/ifu lint cleanup
2021-10-23 12:10:13 -07:00
David Harris
2cfbd888fd
more lsu/ifu lint cleanup
2021-10-23 12:00:32 -07:00
David Harris
11b0607e63
Lint cleanup
2021-10-23 09:06:21 -07:00
David Harris
ac1b1bfbb6
update scripts for handling src/*/* subdirectories
2021-10-23 08:54:29 -07:00
David Harris
f483e8002a
Lint cleanup
2021-10-23 08:39:21 -07:00
David Harris
e2e950ac0f
Cleaned up LINT erors
2021-10-23 06:28:49 -07:00
David Harris
0516ee768b
replaced flopenl with flopenr when clearing to 0
2021-10-18 16:53:18 -07:00
Ross Thompson
cd58a388e4
fixed issues with dc shell not liking modules with parameters without default values.
2021-10-18 17:24:15 -05:00
Ross Thompson
221dbe92b2
Fixed the amo on dcache miss cpu stall issue.
2021-09-17 22:15:03 -05:00
Ross Thompson
e16c27225b
Finished adding the d cache flush. Required ensuring the write data, address, and size are
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correct when transmitting to AHBLite interface.
2021-09-17 13:03:04 -05:00
Ross Thompson
0b1e59d075
Updated Dcache to fully support flush. This appears to work.
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Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
2021-09-17 10:25:21 -05:00
Ross Thompson
615fd41e7b
Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
2021-09-16 18:32:29 -05:00
Ross Thompson
348187ea70
Added counters to walk through d cache flush.
2021-09-16 17:12:51 -05:00
Ross Thompson
d901f60a6d
Added flush controls to cachway.
2021-09-16 16:56:48 -05:00
Ross Thompson
cae350abb7
Added invalidate to icache.
2021-09-16 16:15:54 -05:00
Ross Thompson
5744796431
Fixed dcache to prevent latches in FPGA synthesized design.
2021-09-11 12:03:48 -05:00
Ross Thompson
6f4542f063
Third attempt at fixing the write enables for the icache cacheway.
2021-09-09 15:08:10 -05:00
Ross Thompson
6965bde95c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Refixed some bit width issues in the icache.
2021-09-09 12:44:02 -05:00
Ross Thompson
1d370ca71f
fixed some lint bugs.
2021-09-09 12:38:57 -05:00
David Harris
12bd351edf
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
Ross Thompson
49e75d579c
Set associate icache working, but way 0 is never written.
2021-09-07 12:46:16 -05:00
Ross Thompson
05455f8392
Changed name of memory in icache.
2021-09-06 20:54:52 -05:00
Ross Thompson
2968623f9a
Partial multiway set associative icache.
2021-08-30 10:49:24 -05:00
Ross Thompson
6a9fa2fae3
Fixed bugs I introduced to the icache.
2021-08-27 15:00:40 -05:00
Ross Thompson
d433db3048
Renamed PCMux (icache) to SelAdr to match dcache.
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Removed unused cache files.
2021-08-27 11:14:10 -05:00
Ross Thompson
96cbd8e785
Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm.
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One downside is it increases the icache complexity. However it also fixes an untested bug. If a region
was uncacheable it would have been possible for the request to be made multiple times. Now that is
not possible. Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
2021-08-27 11:03:36 -05:00
Ross Thompson
4ace7fe946
Renamed ICacheCntrl to icachefsm.
2021-08-26 15:57:17 -05:00
Ross Thompson
d6ff89b7e6
Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits.
2021-08-26 15:43:02 -05:00
Ross Thompson
aea7afead6
Finished moving data path logic from the ICacheCntrl.sv to icache.sv.
2021-08-26 13:06:24 -05:00
Ross Thompson
86fc632790
Moved data path logic from icacheCntrl to icache.
2021-08-26 10:58:19 -05:00
Ross Thompson
fd28c4f556
Removed unused logic in icache.
2021-08-26 10:49:54 -05:00
Ross Thompson
e4bbd3bbc7
Converted the icache type from logic to state type.
2021-08-26 10:41:42 -05:00
Ross Thompson
596bc138bc
Forgot to include a few files in the last few commits.
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Also reorganized the dcache by read cpu path, write cpu path, and bus interface path.
Changed i/o names on subwordread to match signals in dcache.
2021-08-25 22:30:05 -05:00
Ross Thompson
0530047f53
Moved dcache fsm to separate module.
2021-08-25 21:37:10 -05:00
Ross Thompson
d23b860c96
Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.
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This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
2021-08-25 21:09:42 -05:00
Ross Thompson
c5e2443298
Replaced dcache generate ORing with or_rows.
2021-08-25 13:46:36 -05:00
