14 Commits

Author	SHA1	Message	Date
bbracker	4e09793a9a	ah merge; I checked and this does pass all of regression except lints	2021-06-25 07:37:06 -04:00
bbracker	aac9b46a1f	changed SC M-to-E fowarding to W-to-E forwarding to improve critical path	2021-06-25 07:18:38 -04:00
Katherine Parry	bc8d660bc5	FPU forwarding reworked pt.1	2021-06-24 18:39:18 -04:00
bbracker	ced5039776	Revert "fixed forwarding" ... This reverts commit 0f4a4a6ade.	2021-06-24 17:39:37 -04:00
bbracker	0f4a4a6ade	fixed forwarding	2021-06-24 11:20:21 -04:00
Katherine Parry	65eca433b6	All compare instructions pass imperas tests	2021-05-27 15:23:28 -04:00
Katherine Parry	03aea055fa	FMV.X.D imperas test passes	2021-05-24 14:44:30 -04:00
James E. Stine	9026357350	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
ushakya22	ba01d57767	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
David Harris	73920282af	Eliminated flushing pipeline on CSR reads	2021-02-26 17:00:07 -05:00
David Harris	cd4ba8831c	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	adc5d5bc1a	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	229bde5953	Moved LoadStall generation to IEU	2021-02-02 13:42:23 -05:00