94 Commits

Author	SHA1	Message	Date
Ross Thompson	6d914def08	Name cleanup.	2022-03-10 18:44:50 -06:00
Ross Thompson	63b1ea88c9	Signal name cleanup.	2022-03-10 18:26:58 -06:00
Ross Thompson	396c97fc36	Byte write enables are passing all configs now.	2022-03-10 17:26:32 -06:00
Ross Thompson	7a129c75cd	Added byte write enables to cache SRAMs.	2022-03-10 15:48:31 -06:00
David Harris	bc2b757952	bit write update	2022-03-09 19:09:20 +00:00
David Harris	27f09ffb33	Refactored SRAM bit write enable	2022-03-09 17:49:28 +00:00
Ross Thompson	3ec32d7ce8	Removed unused signal.	2022-03-08 16:58:26 -06:00
Ross Thompson	d78ba777a4	Added parameter to spillsupport.	2022-03-08 16:38:48 -06:00
Ross Thompson	7b96b3f73c	Moved cacheable signal into cache.	2022-03-08 16:34:02 -06:00
Ross Thompson	730fdb029a	Fixed bug with DAPageFault being wrong when HPTW writes not supported.	2022-02-23 10:54:34 -06:00
Ross Thompson	6f53f7943f	More spillsupport more structual.	2022-02-23 10:27:14 -06:00
Ross Thompson	19ec874641	Fixed bug with spill support and Instruction DA Page Faults.	2022-02-23 10:16:12 -06:00
Ross Thompson	15f6871a8d	Added generates to pcnextf muxes for privileged and caches.	2022-02-22 22:45:00 -06:00
Ross Thompson	59f04f2518	Minor busdp cleanup.	2022-02-22 17:28:26 -06:00
Ross Thompson	8a280f211f	Annotated IFU for mux changes.	2022-02-21 17:20:34 -06:00
Ross Thompson	565ca4e4a3	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
Ross Thompson	beac362364	Moved a few muxes around after sww changes.	2022-02-16 15:43:03 -06:00
Ross Thompson	6a2bcfcd01	cleanup of signal names.	2022-02-16 15:29:08 -06:00
David Harris	1d5c8a7b98	t push ... Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-14 01:22:22 +00:00
Ross Thompson	7ffbc6b2ab	Changed names of signals in cache.	2022-02-13 15:06:18 -06:00
David Harris	b360e7b941	Synthesis cleanup	2022-02-12 06:25:12 +00:00
Ross Thompson	febd019854	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-11 10:47:21 -06:00
Ross Thompson	6d12010d02	Fixed subtle and infrequenct bug. ... Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.	2022-02-11 10:46:06 -06:00
David Harris	de5e80696d	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
Ross Thompson	689c32215f	Fixed bugs in ifu spills and missing reset on bus data register.	2022-02-10 18:11:57 -06:00
Ross Thompson	104a9acf81	Cleanup.	2022-02-10 11:27:15 -06:00
Ross Thompson	fdb4f909fc	Cleanup + critical path optimizations.	2022-02-10 11:11:16 -06:00
Ross Thompson	36ab78ef3b	Removed all possilbe paths to PreSelAdr from TrapM.	2022-02-09 19:20:10 -06:00
Ross Thompson	c2907ec0f4	Cleanup IFU.	2022-02-08 14:54:53 -06:00
Ross Thompson	e02bc8db67	rv32e works for now. Still need to optimize.	2022-02-08 14:21:55 -06:00
Ross Thompson	f211fe635a	Moved some muxes back into the bp.	2022-02-08 14:17:44 -06:00
Ross Thompson	aa12d90272	Temporary commit which gets the no branch predictor implementation working.	2022-02-08 14:13:55 -06:00
Ross Thompson	8a2ee22395	Finished merge.	2022-02-08 11:36:24 -06:00
David Harris	9b55848ffc	Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration	2022-02-06 01:22:40 +00:00
Ross Thompson	ea84211ff9	Removed unused ports from caches and buses.	2022-02-04 22:52:51 -06:00
Ross Thompson	011ad09341	Cleanup.	2022-02-04 22:40:51 -06:00
Ross Thompson	4074f695e0	Moved the hwdata mux back into the busdp.	2022-02-04 22:39:13 -06:00
Ross Thompson	40eb055861	Merged together the two sub cache line read muxes. ... One mux was used for loads and the other for eviction.	2022-02-04 22:30:04 -06:00
David Harris	72bc64ef28	Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.	2022-02-05 04:16:18 +00:00
Ross Thompson	290430cda8	Moved the sub cache line read logic to lsu/ifu.	2022-02-04 20:42:53 -06:00
David Harris	da8819d64b	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
Ross Thompson	6c5b0bec40	More cleanup of IFU.	2022-02-01 14:32:27 -06:00
Ross Thompson	1f0821da0d	IFU and LSU now share the same busdp module.	2022-01-31 16:25:41 -06:00
Ross Thompson	86bac2a083	partial ifu cleanup.	2022-01-31 16:08:53 -06:00
Ross Thompson	e4ee630a3e	cleanup.	2022-01-31 13:29:04 -06:00
Ross Thompson	a4f6653cd8	Encapsulated the bus data path into a separate module.	2022-01-31 10:15:48 -06:00
Ross Thompson	ac50a36aac	LSU and IFU cleanup.	2022-01-28 15:26:06 -06:00
Ross Thompson	2e00186eea	Updated wave.do to match the ifu/lsu changes.	2022-01-28 14:37:15 -06:00
Ross Thompson	42d60235f0	Clean up of mmu instances in IFU and LSU.	2022-01-28 14:02:05 -06:00
Ross Thompson	c5e0024e9f	Moved spills to own module.	2022-01-28 13:40:35 -06:00