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Author	SHA1	Message	Date
bbracker	6d7bc928af	update SXL UXL bits in MSTATUS to match new QEMU trace	2022-03-02 22:15:57 +00:00
bbracker	e9e827c83e	add CSRs to waveview	2022-03-02 18:31:10 +00:00
bbracker	4fe35aadf2	add rv32a tests to regression	2022-03-02 17:54:55 +00:00
bbracker	7d7a4fefb3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-02 17:46:40 +00:00
bbracker	1bb73dad7d	change main.config so that buildroot expects linux.config and busybox.config to be at $RISCV/buildroot	2022-03-02 17:46:33 +00:00
David Harris	6413f71541	removed imperas-riscv-tests	2022-03-02 17:28:55 +00:00
David Harris	c543fedc60	removed imperas-riscv-tests	2022-03-02 17:28:20 +00:00
bbracker	b6031bb15f	fix buildroot checkpointing and add it back to regression	2022-03-02 16:00:19 +00:00
bbracker	29179c6787	add LRSC test and add wally64a to regression	2022-03-02 07:09:37 +00:00
bbracker	e3ae7fabc7	fix AMO test	2022-03-02 05:41:20 +00:00
David Harris	0ecfff7e3a	FMA project ready to start	2022-03-01 20:58:08 +00:00
David Harris	0693f76676	Fixed march compiling privileged tests to support AMO tests.	2022-03-01 18:02:45 +00:00
bbracker	eaa0fa8e3f	checkpoint sweep script -- not sure if this deserves to be on the repo in the long run, but it is helpful	2022-03-01 03:48:31 +00:00
bbracker	3eb229cda5	copy over truncated trace into checkpoint if not freshly generating a trace	2022-03-01 03:38:48 +00:00
bbracker	d2fa5fa645	buildroot graphical sim bugfix	2022-03-01 03:24:23 +00:00
bbracker	da4d7de2bd	add option to not generate a trace when making checkpoints	2022-03-01 03:13:01 +00:00
bbracker	a8e8cfb838	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
bbracker	a048dbb86b	remove old testvector-generation folder	2022-03-01 01:46:26 +00:00
bbracker	00ae804b6c	script for dumping out QEMU ram and bootrom state at ground 0	2022-03-01 01:45:09 +00:00
bbracker	eb26bf69ca	typo fix to checkpoint generator	2022-03-01 00:51:54 +00:00
bbracker	f63c3264c2	tentatively add WALLY-AMO test to arch test infrastructure	2022-03-01 00:40:11 +00:00
bbracker	d8ddda760b	deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test	2022-03-01 00:37:46 +00:00
bbracker	ce2fe16243	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-28 23:00:07 +00:00
bbracker	7af81d93ec	greatly improve trace-generating checkpoint process with QEMU hack	2022-02-28 23:00:00 +00:00
bbracker	3f5ae216b5	change pipe silencer to redirect to stderr so that we can see if QEMU is at least still alive	2022-02-28 22:55:23 +00:00
David Harris	329fea9329	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
David Harris	e2abc79f1d	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-28 20:34:35 +00:00
David Harris	5faf52ae87	fpcalc Makefile	2022-02-28 20:34:33 +00:00
David Harris	2ea93c4ac3	adrdecs comments	2022-02-28 20:33:41 +00:00
James E. Stine	eba4eda245	Minor tweak of output of fpcalc - can be reversed with commented out code	2022-02-28 14:10:22 -06:00
Kip Macsai-Goren	f14acac1bf	Changed PMA tests to only allow native length accesses to CLINT	2022-02-28 19:22:44 +00:00
Kip Macsai-Goren	0715c62de5	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-28 19:14:18 +00:00
David Harris	908349cbde	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-28 19:13:54 +00:00
David Harris	2de31a15da	Modified address decoder for native access to CLINT	2022-02-28 19:13:14 +00:00
Shreya Sanghai	6a1f1e2496	changed filename	2022-02-28 17:33:15 +00:00
Shreya Sanghai	06c2744ac1	Copied previous cofig file instead of orig	2022-02-28 17:32:08 +00:00
Shreya Sanghai	db38b69f83	Makefile for running multiple synthesis	2022-02-28 17:15:43 +00:00
Shreya Sanghai	5b30fb7328	added make allsynth	2022-02-28 17:15:43 +00:00
David Harris	3a43450ac9	hptw cleanup for synthesis	2022-02-28 05:54:34 +00:00
David Harris	9b4d6427f4	Corrected printing doubles	2022-02-28 04:28:07 +00:00
David Harris	9ca4942994	ZMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-28 04:15:23 +00:00
David Harris	0cc09ed918	Enhanced printing intermediate results in fpcalc.c	2022-02-28 04:15:20 +00:00
Kip Macsai-Goren	6f701a16b3	added snippet to ignore comments in .diff files as well	2022-02-27 23:29:46 +00:00
Kip Macsai-Goren	369e799ce3	added minor sections to MMU tests that had been missing, global bits still need to be checked	2022-02-27 23:28:44 +00:00
David Harris	50f5607799	New softfloat_calc program	2022-02-27 20:35:01 +00:00
David Harris	f4be78ecc3	Created softfloat_demo showcasing how to do math with SoftFloat	2022-02-27 18:17:21 +00:00
David Harris	dbd73e8cfd	Moved regression work directories to regression/wkdir to reduce clutter	2022-02-27 17:35:09 +00:00
David Harris	3675a813c6	Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior	2022-02-27 17:23:33 +00:00
David Harris	62d62f9a9e	Moved FMA back into source tree to facilitate synthesis	2022-02-27 15:41:41 +00:00
David Harris	5b15e552c6	Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue	2022-02-27 15:12:10 +00:00