71 Commits

Author	SHA1	Message	Date
Victor Clements	e3856708d0	pulling in FreeRTOS/kernel Submodule	2023-06-13 10:41:18 -07:00
David Harris	d4d9fa1ff6	wally installation improvements: latest main branch of riscv-arch-test, updated install script	2023-05-10 08:23:55 -07:00
Ross Thompson	fc9081b64c	Added Yujun Lin's branch predictor simulator. This is a C baseline module for common branch predictor algorithms.	2023-03-07 10:49:59 -06:00
David Harris	bd6a1dcf40	Pulled to latest commit of riscv-arch-test	2023-02-28 15:03:59 -08:00
James Stine	704542d813	Update Appendix D + wrapped memories	2023-01-28 19:46:43 -06:00
David Harris	52626d78d5	Removed old link to imperas-riscv-tests	2023-01-26 14:53:25 -08:00
James Stine	b0f6582d26	This adds the Dockerfile for those who might be interested in building a docker container for Wally	2023-01-23 17:29:58 -06:00
David Harris	16f3c25cb7	sram1p1rw cleanup	2022-12-20 02:57:51 -08:00
Ross Thompson	128b3d20e7	Updated riscv arch test removed misaligned1.	2022-12-04 00:18:10 +00:00
David Harris	22455f7743	embench cleaned up	2022-09-08 11:38:01 -07:00
Katherine Parry	bd336f18b3	merged radix-2 sqrt into divider - doesnt work yet	2022-07-23 00:41:18 +00:00
slmnemo	49565f944c	Added PLIC and UART tests and new functions to the test library	2022-07-22 07:10:39 -07:00
Daniel Torres	28c61a2191	changed gitignore, updated version of arch tests on main build	2022-07-21 21:10:15 -07:00
Katherine Parry	270216dd02	radix-4 division integrated into srt - not tested	2022-07-21 19:38:06 +00:00
Daniel Torres	e9aedfdc53	changed the default branch of embench	2022-07-21 10:14:05 -07:00
David Harris	149301db32	Removed Sky130 libraries	2022-07-06 13:50:11 +00:00
Katherine Parry	254ebf478e	added fld in rv32 - needs testing	2022-06-20 22:53:13 +00:00
Madeleine Masser-Frye	ab7c936788	remove run deletion with wally synthesis	2022-06-17 19:45:38 +00:00
DTowersM	919c1818a8	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-06-13 23:34:35 +00:00
DTowersM	1f4d56ba32	added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)	2022-06-13 23:23:57 +00:00
Katherine Parry	31fd8772cf	postprocessing unit created and passing all tests	2022-06-13 22:47:51 +00:00
Madeleine Masser-Frye	1bf1a6d3a5	update	2022-06-03 21:17:50 +00:00
Katherine Parry	4ed7933aa3	added unpackinput.sv	2022-05-31 16:18:50 +00:00
Madeleine Masser-Frye	8506d98bec	added optimized area plotting	2022-05-30 18:54:02 +00:00
Katherine Parry	950a17bef5	fixed lint error	2022-05-28 10:20:13 -07:00
Madeleine Masser-Frye	ab0b0a0da4	fixed normalization vertical axes, added TechSpecs type	2022-05-28 04:57:18 +00:00
Katherine Parry	a0ff98042c	unpacker adds 1 to denorm expoents	2022-05-27 14:37:10 -07:00
Katherine Parry	95b506c5e0	some optimizations in unpacker	2022-05-27 11:36:04 -07:00
cturek	4a4f153eef	Set up the divider for on-the-fly conversion	2022-05-26 16:45:28 +00:00
Katherine Parry	f3b28b988b	added fcvt.sv	2022-05-26 00:10:51 +00:00
cturek	51debfa186	Fixed exponent verification, added sign module and added sign tests	2022-05-25 23:36:21 +00:00
Katherine Parry	f35450207f	single and double conversions pass all tests	2022-05-25 23:02:02 +00:00
Madeleine Masser-Frye	dbe4b4bafa	added widths for csa in ppa	2022-05-22 23:23:02 +00:00
Katherine Parry	5d34db85b2	Fixed unpacker bug LT EQ LE pass testfloat	2022-05-20 17:19:50 +00:00
Madeleine Masser-Frye	8015b6af17	fixed dynamic energy units	2022-05-20 01:59:19 +00:00
Katherine Parry	738bbf6479	Added fp tests - doesnpass yet	2022-05-19 16:32:30 +00:00
mmasserfrye	a10b8e47af	cleaned lint for ppa.sv	2022-05-12 20:20:05 +00:00
David Harris	f17501ed8c	Removing unused signals	2022-05-12 14:36:15 +00:00
mmasserfrye	6cba6a92ba	filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv	2022-05-12 07:22:06 +00:00
Ross Thompson	b3153bc71e	Updated wally to point to riscv-arch-test tag 2.7.3	2022-04-16 15:32:43 -05:00
Katherine Parry	74e0db04ac	fixed errors and warnings in rv32e	2022-04-07 17:21:20 +00:00
David Harris	c4f2c6b110	fpu compare simplification, minor cleanup	2022-03-29 17:11:28 +00:00
Katherine Parry	e3d01c875b	FMA parameterized and FMA testbench reworked	2022-03-19 19:39:03 +00:00
David Harris	ff674b695c	Moved Softfloat / TestFloat	2022-02-26 19:17:32 +00:00
James Stine	60e19e3b67	Added the 12T submodule to the project.	2022-02-03 19:26:41 -06:00
David Harris	96a0baade4	Removed soc_flow	2022-01-31 22:58:33 +00:00
David Harris	090533cfe9	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
David Harris	3016b46d65	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-31 00:59:49 +00:00
David Harris	71f7d66dbf	gitmodules	2022-01-31 00:59:44 +00:00
James Stine	8fd975da74	Remove book_flow to add back later - will add synthDC back within 30m	2022-01-28 08:18:30 -06:00