27 Commits

Author	SHA1	Message	Date
David Harris	b7f579a146	csr cleanup	2023-01-13 21:29:03 -08:00
David Harris	c5358da771	csr cleanup	2023-01-13 21:25:55 -08:00
David Harris	9da2fae1f3	csr comments	2023-01-13 20:49:34 -08:00
David Harris	370678f730	trap comments	2023-01-13 19:44:38 -08:00
David Harris	e67f125201	Header comments	2023-01-12 04:35:44 -08:00
David Harris	7d93659f6b	changed name to CORE-V-WALLY	2023-01-11 15:15:08 -08:00
David Harris	b911056e66	Changed Wally to CORE-V Wally	2023-01-11 14:03:44 -08:00
David Harris	e92cffbb5e	Changed MIT license to Solderpad License	2023-01-10 11:35:20 -08:00
David Harris	85d0b697bf	Removed unused StallW from CSRs	2022-12-23 00:21:36 -08:00
David Harris	93bb8036be	Revert to 98b824	2022-12-22 23:58:14 -08:00
David Harris	51b92285d3	Removed unused signals in FPU and CSR	2022-12-22 22:59:05 -08:00
David Harris	ca949f2110	Only delegated bits of SIP are readable	2022-12-21 12:32:49 -08:00
David Harris	877c4eefd1	Fixed typo in csrm	2022-05-12 06:55:39 -07:00
David Harris	32f8841f79	Added MCONFIGPTR CSR hardwired to 0	2022-05-12 04:31:45 +00:00
David Harris	8066ba45e8	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
David Harris	0ede295e88	Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields	2022-04-25 14:49:00 +00:00
David Harris	851d5e8c5e	Added MTINST hardwired to 0, and added timeout of U-mode WFI	2022-04-24 20:00:02 +00:00
Ross Thompson	0340c0fd44	Added wave config ... added new signals to ILA.	2022-04-01 12:44:14 -05:00
bbracker	54b9745a75	big interrupts refactor	2022-03-30 13:22:41 -07:00
David Harris	d8170e9dd3	Mostly removed N_SUPPORTED	2022-02-15 19:50:44 +00:00
David Harris	c12407ba6a	Removed Busybear dependencies	2022-02-02 20:28:21 +00:00
Ross Thompson	ec44774c77	Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv	2022-01-20 16:39:54 -06:00
Ross Thompson	5cf686429d	Merged in the debug ila updates.	2022-01-18 17:29:21 -06:00
Ross Thompson	fdc17f5017	Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.	2022-01-18 17:19:33 -06:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	d66f7c841b	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00